Alcatel

Alcatel Sel Aktiengesellschaft

Henry W Owen

Michael Joachim Wolf

Ellen Witte Zegura

Peter E Sholander

Won Bae Park

Chris B Autry

An apparatus, to be used in a desynchronizer, for minimizing the output jitter of the desynchronizer. The desynchronizer is assumed to include a bit buffer for staging data that is to be output. The desynchronizer is also assumed to include a means for decoding the input signal to determine how justification opportunities in the input signal are used and therefore what justification bits must be leaked by the desynchronizer. The apparatus and method of the present invention uses the information about the incoming justification bits or incoming justification bytes and the state of the buffer to determine the longest possible time to wait before issuing a command to momentarily speed up or delay outputting the next data unit from the bit buffer. This speeding up or delay is caused by sending a clock signal to the bit buffer that is shifted in phase by a small amount, thereby spreading out the effect of an incoming positive or negative justification bit or byte over many periods of the output clock of the desynchronizer.

Apparatus for reducing jitter in a desynchronizer

A connection procedure for finding by rearrangement a path for multirate, multicast traffic through an SDH cross-connect with subnetwork connection protection. If no free path for a new payload through the SDH switching hardware is available, the switching procedure looks for a path that is adequate and blocked by the least existing payload capacity. If the hunt is successful, the procedure rearranges the existing connections to make possible a path for the new payload. The procedure does not interrupt the existing connections; thus it is a 'hitless' procedure. Connections for existing payloads that must be moved to make way for the new payload are queued and the connection procedure is applied recursively, to each in turn, until the queue is empty.

Cross-connect multirate/multicast SDH/SONET rearrangement procedure and

A synchronous digital transmission system has network nodes each operating at a respective fixed internal clock rate, each with a justification device for adapting an incoming signal to the respective fixed internal clock rate thereof by positive or negative justification actions, and for controlling a memory device which stores payload bytes of a frame of the incoming signal and outputs the payload bytes at the internal clock rate of a respective network node. The justification device has a first circuit (10) for counting incoming/outgoing frame bytes and calculating at sampling instants (T.sub.i) a difference value (.DELTA..sub.i) and a change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i), has a second circuit (20) for calculating a control value (OFFSET) which is dependent on the change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i) and on a correction factor (LEAK), and has a third circuit (30) for comparing at the sampling instants (T.sub.i) the control value (OFFSET) with an upper threshold (U.sub.-- THRESH) and a lower threshold (L.sub.-- THRESH), and for initiating either a positive or negative justification action respectively if the control value (OFFSET) is either less than the lower threshold (L.sub.-- THRESH) or greater than the upper threshold (U.sub.-- THRESH).

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Smyrna, GA, United States of America

Henry W Owen