Other

Aip Semi, Inc.

Henry Verheyen

Jianjun Wen

A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Hardware architecture for processing data in neural network

A secure data exchange system permits device to exchange secure message keys and securely transmit messages between devices. The devices may initially exchange temporary message keys that are used to encrypt permanent message keys. In addition, devices may have pairing managed that authenticates devices. Devices may be associated with an address ledger that maintains address information and is accessible with a public ledger key, which may provide different access to address information to different paired devices. Data within the system may also be encrypted with user device keys that prevents unauthorized access to data while permitting recreation of the user device key for data backup and migration.

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Marina, CA, United States of America

Henry Verheyen