Texas Instruments Corporation

Henry T Yung

William Robert Krenik

Steve Wiyi Yang

Eric G Soenen

James R Hellums

Louis J Izzi

Karl M Guttag

Richard D Simpson

James Robert Hochschild

Jeffrey L Nye

Jerry R Van Aken

Ching-yuh Tsay

James E Chloupek

Chenwei J Yin

Carrell R Killebrew, Jr

Michael Joseph Tsecouras

William A Severin

Mike Asal

Michiel deWit

A multiplier circuit multiplies a reference voltage to increase the level of the reference voltage. A feedback circuit of the multiplier circuit stabilize the multiplier circuit such that a feedback voltage of said feedback circuit tends to equalize the reference voltage. The feedback circuit is free from capacitance which would unstabilize the feedback circuit. A voltage divider outside of the feedback circuit reduces the multiplied voltage of the multiplier circuit.

Multiplier circuit

A voltage reference circuit includes: an amplifier A1 with low open loop output impedance, an output of the amplifier is coupled to a first input of the amplifier A1; and a first resistor R1 coupled between the output of the amplifier A1 and a reference node 30, the first resistor R1 has a resistance substantially equally to the low open loop output impedance, whereby a low frequency impedance at the reference node 30 is substantially equal to the resistance.

Low-noise low-impedance voltage reference

A digital-to-analog converter includes a first array of resistors 10-16 connected in series; a switch matrix 20 coupled to the first array of resistors 10-16; a first variable resistor RTOP coupled to a first end of the first array of resistors 10-16; and a second variable resistor RBOT coupled to a second end of the first array of resistors 10-16, the first variable resistor RTOP and the second variable resistor RBOT having a combined resistance that is a fixed resistance value.

Resistor string digital-to-analog converter

The current-integrating analog-to-digital converter includes a first charge storage device C.sub.1 ; a second charge storage device C.sub.2 ; an input current I.sub.in coupled to the first charge storage device C.sub.1 for a first time period; a variable reference current I.sub.dac coupled to the second charge storage device C.sub.2 for a second time period; and a comparator 20 for comparing the voltage on the first charge storage device C.sub.1 with the voltage on the second charge storage device C.sub.2.

Current-integrating successive-approximation analog-to-digital converter

A System and method for calibrating a chip after packaging including providing a packaged chip, providing programmable non-volatile storage having a plurality of non-volatile storage elements in the chip and providing a volatile storage having a plurality of volatile storage elements in the chip with one volatile storage element associated with one non-volatile storage element. The chip includes circuitry responsive to a predetermined signal to permit the non-volatile storage to be programmed in accordance with data stored in the volatile storage and to a predetermined signal to prevent external alteration of the non-volatile storage. The non-volatile storage is preferably a plurality of fuses. The volatile storage is preferably a shift register. The circuitry in the chip includes a bistable device responsive to the predetermined signal to assume a first condition to permit the non-volatile storage to be programmed and responsive to the alteration of the predetermined signal to assume a second condition which does not allow alteration of data. The system further includes a non-volatile storage element settable to one of a first or a second condition and preset to the first condition, the circuitry in the chip responsive to the first condition to permit the non-volatile storage to be programmed in accordance with data stored in the storage and responsive to the second condition to prevent external alteration of the non-volatile storage. The condition of the non-volatile element determines whether or not the first state (program) of the bistable device can be entered.

Method for programming permanent calibration information at final test

A circuit includes a first transistor M.sub.1 ; a second transistor M.sub.2 having a gate coupled to a gate of the first transistor M.sub.1 and a source coupled to a source of the first transistor M.sub.1 ; a third transistor M.sub.3 having a source coupled to a drain of the first transistor M.sub.1 and a drain coupled to a current input I.sub.b, the drain of the third transistor M.sub.3 is coupled to the gate of the first transistor M.sub.1 ; a fourth transistor M.sub.4 having a source coupled to a drain of the second transistor M.sub.2, a gate coupled to a gate of the third transistor M.sub.3, and a drain coupled to a supply node V.sub.DD ; and a variable voltage input V.sub.x coupled to the gate of the third transistor M.sub.3.

MOS current mirror capable of operating in the triode region with

The circuit for generating current has a controllable current source M.sub.7, an input transistor pair 24 having a first branch and a second branch, a current mirror 28 having a first branch and a second branch, and an amplifier 50. The controllable current source M.sub.7 is coupled to the first and second branches of the input transistor pair 24. The first branch of the current mirror 28 is coupled to the first branch of the input transistor pair 24. The second branch of the current mirror 28 is coupled to the second branch of the input transistor pair 24. The input transistor pair 24 is coupled between the controllable current source M.sub.7 and the current mirror 28. The amplifier 50 has an output coupled to the controllable current source M.sub.7, and a first input coupled to the second branch of the input transistor pair 24 and the second branch of the current mirror 28.

Circuitry for bias current generation

An integrated circuit capacitor has a semiconductor die and a plurality of field effect transistors fabricated on the die and having gates, sources and drains. The gates are connected to each other as one side of the capacitor. The sources and drains are connected together as another side of the capacitor. A color palette has a die with circuitry including a dot clock buffer with transistors connected to supply rails and the integrated circuit capacitor having a plurality of the parallel-connected field effect transistors connected across the supply rails. The dot clock buffer has an output distributed directly to the rest of the circuitry. Other capacitors, buffers, systems and methods are also disclosed.

Integrated circuit capacitors, buffers, systems and methods

A circuit for adjusting capacitors in a capacitor analog to digital converter has a main capacitor array including more than one capacitor array portion 20 and 22, and at least one first coupling capacitor C.sub.c. A first plate of each first coupling capacitor C.sub.c is coupled to one capacitor array portion 22 and a second plate of each first coupling capacitor C.sub.c is coupled to a next more significant capacitor array portion 20 such that each capacitor array portion is coupled to the next more significant capacitor array portion by one of the first coupling capacitors C.sub.c. The circuit has at least one second coupling capacitor C.sub.c3 with a first plate of each second coupling capacitor C.sub.c3 coupled to the first plate of a corresponding one of the first coupling capacitors C.sub.c. The circuit also has at least one array of calibration capacitors 60-84 with first plates of each array of calibration capacitors 60-84 coupled to a second plate of a corresponding one of the second coupling capacitors C.sub.c3 and second plates of each array of calibration capacitors 60-84 coupled to corresponding switches 100-124. Switch control signals S.sub.c4, S.sub.c3, S.sub.c2, S.sub.c1, and S.sub.c0, and S.sub.4, S.sub.3, S.sub.2, S.sub.1, and S.sub.0 control the switches such that each switch connects the corresponding calibration capacitor to either a first node V.sub.ref+ or a second node V.sub.ref-. Each switch control signal consists of two switch control bits which are combined by a logic function.

Methods for adjusting the coupling capacitor of a multi-stage weighted

A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.

Video interface palette, systems and method

A multi-mode analog to digital converter is described for converting an analog input into a digital value according to a linear or a companding transfer function. The converter comprises a comparator, a successive approximation register and a charge redistribution device. The comparator compares the input voltage and a generated voltage. The successive approximation register generates a provisional binary word responsive to the output of the comparator. The charge redistribution device generates the generated voltage according to the provisional binary word and to a selected transfer function. The transfer function may be selected from the group consisting of linear and companding.

Linear/companding A/D converter

A CMOS on chip mid-rail voltage generation circuit is provided for an analog ground reference. A voltage divider establishes a current path between the high and low rail, and supplies a mid-level voltage to one input of a differential amplifier. A pair of series connected field effect transistors are also connected between the high and low voltage rails, with their common connection providing the input to the other input of the differential amplifier. A pair of open loop output transistors are also coupled in series between the high and low voltage rails, and each has their gate coupled to one of the series connected pair, and is also matched to that pair.

CMOS integrated mid-supply voltage generator

Apparatus for enhancing capacitance matching in a multi-stage capacitor network of an A/D converter is provided. The stages are coupled to one another by a coupling capacitor having a top and bottom plate. The apparatus comprises a first shield overlying the capacitor network, where the shield is coupled to a known potential. A second shield is positioned over each of the coupling capacitors, where each second shield is separate from the first shield and coupled to the bottom plate of each respective coupling capacitor.

Apparatus and method for enhancing capacitance matching in a multi-stage

A TTL compatible CMOS high-speed lower-power supply-independent input buffer has a first current mirror which supplies current to a reference node of the input buffer when the signal at the input node of the buffer goes to a high state. An MOS transistor has its gate connected to the input node and switches hard on when the input node goes to a high level, pulling the reference node to a low level. A second current mirror is provided which injects current into the reference node for a predetermined period of time after the voltage level at the input of the buffer goes to a low level to pull the reference node to a high level. Both the first and second current mirror are switched on only during transition states of the input buffer, to minimize power dissipation when the input buffer is in its quiescent state.

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Richardson, TX, United States of America

Henry T Yung