Infineon Technologies Ag

Infineon Ag

Advanced Memory International, Inc.

Polaris Innovations Limited

Henry Stracovsky

Piotr Szabelski

Brent Keeth

Troy A Manning

Peter B Gillingham

Terry R Lee

Kevin J Ryan

David V James

Cormac Michael O'Connell

Bruce Millar

Yoshikazu Morooka

Desi Rhoden

Donald N North

Hans A Wiggers

David B Gustavson

Jean Crepeau

According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus.

Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory

According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page timers such that each of the page timers store a period of time between a last issued command to the particular page and a predicted next access to the memory, wherein the next access to the same page can be &ldquo;close&rdquo;, &ldquo;open&rdquo;, &ldquo;write&rdquo; or &ldquo;read&rdquo;. An incoming new command is received and it is then determined how long a particularly page access has to wait before the issue. An appropriate contents of a command timing lookup table is selected by the new command. A new time value is written into appropriate page timers that has to be inserted between the new command and a possible next access to the same page.

Methods and apparatus for prediction of the time between two consecutive memory accesses

A universal access controller is described. The universal resource access controller is coupled to a requesting system and a resource, such that when the requesting system desires access to the resource, the requesting system generates a resource access request which is passed to the universal resource controller. The universal resource controller, in turn, uses a specific characteristic operating parameter of the requested resource as well as a current state of the requested resource to generate a corresponding sequenced universal access request command suitable for accessing the resource as required by the requesting system.

Universal resource access controller

According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests are described. In one embodiment, a method of increasing data bandwidth by reordering incoming memory requests in order to avoid gaps between commands on a command bus and data packets on a data bus while maintaining the original incoming memory request order is disclosed. A best position in a command queue is calculated for each new incoming command by a reordering block coupled to the command queue. Read data is stored in a data queue while the associated incoming commands are stored in their respective original order in a FIFO register included in a re-reordering block. The data is stored in its original order in a data queue while incoming data from the memory is stored in a read-data buffer included in the re-reordering block according to the order stored in the data queue. The stored commands are sent to the processor according to the order stored in the FIFO such that the data to the processor will be issued in the same order as incoming from processor commands.

Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests

A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

Using of bank tag registers to avoid a background operation collision in memory systems

A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

According to the present invention, methods and apparatus for reducing memory access latency are disclosed. When a new entry is made to translation look aside buffer, the new TLB entry points to a corresponding TLB page of memory. Concurrently with the updating of the TLB, the TLB page is moved temporally closer to a processor by storing the TLB page in a TLB page cache. The TLB page cache is temporally closer to the processor than is a main memory.

Techniques for improving memory access in a virtual memory system

According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of requesting device requests of the external devices, a request queue controller unit coupled to the request queue suitably arranged to fetch any of the requests stored therein, a responds queue suitably arranged to store any number of responses from the external devices. The apparatus also includes a responds queue controller unit coupled to the responds queue suitably arranged to fetch any of the requests stored therein; wherein each of the responds and its associated request have associated with them a group identification number indicating a particular group of requesting devices from which the request originated and the corresponding response is destined, wherein the responds queue controller and the request queue controller units use a priority number stored in a group priority selector register to prioritize each of the stored requests and responses, such that a request or response having a higher priority bypasses a request or response having a lower priority.

Methods and apparatus for prioritization of access to external devices

According to the present invention, a scheduler that uses a timing-look-up-table and page timers to determine the time between two consecutive memory accesses is described. The scheduler for scheduling a plurality of commands to an associated memory, the memory comprising a plurality of M memory banks and a plurality of N memory pages includes restriction circuitry for determining an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank and reordering circuitry for determining an order in which the commands should be transmitted to the associated memory with reference to the earliest issue time associated with each command and a data occurrence time associated with selected ones of the commands.

Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses

According to the present invention, a method for controlling access to a memory device is disclosed. A requesting system is identified, the configurable system interface is then configured in order to accommodate the identified requesting system and a memory access request is generated by the requesting system. A universal command is generated by the configurable system interface based upon the memory access request which is then converted from the universal command to a sequenced universal command by the command sequencer based upon both the current state of the memory device as indicated by the corresponding resource tag and the operating characteristic of the memory as indicated by the corresponding the characteristic operating parameter. The memory is then accessed using the sequenced universal command.

Universal memory controller

Computer memory conflict avoidance using a plurality of page registers coupled individually to a plurality of memory banks is described. An incoming system address request containing a requested memory bank number and a requested page number is received by the memory controller. The page register number corresponding to the requested memory bank is located and the open page address in the located page register is compared to the requested page address. If the requested page number corresponds to the open page address, it is then accessed. If it does not match, the memory page corresponding to the requested page address is closed, the memory page corresponding to the requested page address is opened and then accessed.

Computer memory conflict avoidance using page registers

A method of using a reduced number of page tag registers to track a state of physical pages in memory systems are is described. An incoming system address request is received that includes a requested bank number and a requested page number. A page register located in memory controller corresponding to the requested bank number is then located and the stored page address included in the located page register is then compared to the requested page address. The requested page in the memory bank corresponding to the requested bank number is then accessed when the stored page address matches the requested page address for the requested memory bank. The stored page using page address from the page register of the bank which number is given by random page register number generator is closed if the requested bank and stored page address do not match. However, a new page using the page address from the incoming system address is opened after which the requested bank is accessed. Furthermore, the memory controller includes an adjustable comparator unit coupled to each of the plurality of page registers.

Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M

Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution

According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of reqeusting device requests of the external devices, a request queue controller unit coupled to the request queue suitably arranged to fetch any of the requests stored therein, a responds queue suitably arranged to store any number of responses from the the external devices. The apparatus also includes a responds queue controller unit coupled to the responds queue suitably arranged to fetch any of the requests stored therein; wherein each of the responds and its associated request have associated with them a group identification number indicating a particular group of requesting devices from which the request originated and the corresponding response is destined, wherein the responds queue controller and the request queue controller units use a priority number stored in a group priority selector register to prioritize each of the stored reqeusts and responses, such that a request or response having a higher priority bypasses a request or response having a lower priority.

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San Jose, CA, United States of America

Henry Stracovsky