Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Pairgain Technologies, Inc.

Broadcom Corproation

Henry Samueli

Mehdi Hatamian

Oscar Ernesto Agazzi

John L Creigh

Arthur Abnous

David E Kruse

Fang Lu

Thomas J Quigley

Jonathan S Min

Lisa Voigt Denney

Christopher R Jones

Feng Chen

Sean Francis Nazareth

Arya Behzad

Ramon Alejandro Gomez

Klaas Bult

Tom W Kwan

Chi-Hung Lin

Charles P Reames

Avanindra Madisetti

Loke Kun Tan

Jeffrey Scott Putnam

Theodore F Rabenko

Alan Y Kwentus

James C H Thi

John D Horton, Jr

Tarek Kaylani

Thomas D Kwon

Joseph I Laskowski

Jeyhan Karaoguz

Nambirajan Seshadri

Mark Berman

Kenneth R Kindsfater

Joseph Leonard Laskowski

Joseph J Laskowski

Ralph H Brackert

A system and method for updating advertising content for a recorded program (e.g., recorded on personal video recorder equipment), substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

System and method for updating advertising content for a recorded program

A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations.

Robust techniques for upstream communication between subscriber stations and a base station

Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Gigabit ethernet transceiver with analog front end

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements

Method and device for multi-dimensional processing using a single-state decision feedback equalizer

Systems for recovering communicated information in a communication system are disclosed and may include at least one digitizer for digitizing an analog received signal comprising the communicated information, thereby creating a digital received signal. The system may include at least one filter for bandwidth-limiting at least a portion of the digital received signal. At least one feed forward equalizer may be used for equalizing at least a portion of the bandwidth-limited signal to create an equalized signal. At least one converter for creating a data signal according to at least the equalized signal. At least one soft decision circuit for creating a soft decision signal according to the data signal. The soft decision circuit may cancel at least a portion of the equalized signal.

Apparatus for, and method of, processing signals transmitted over a local area network

Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency individual to the TV station being received. They are mixed with signals from a variable frequency oscillator to produce signals at a particular intermediate frequency (IF). An analog-digital converter (ADC) converts the IF signals to corresponding digital signals which are demodulated to produce two digital signals having a quadrature phase relationship. After being filtered and derotated, the digital signals pass to a symmetrical equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) connected to the FFE in a feedback relationship. The DFE may include a slicer providing amplitude approximations of increasing sensitivity at progressive times. Additional slicers in the equalizer combine the FFE and DFE outputs to provide the output data without any of the coaxial cable noise or distortions. The equalizer outputs and initially the derotation outputs, and the slicer outputs, servo (1) the oscillator frequency to obtain the IF frequency, (2) the ADC sampling clock to obtain the digital conversion at a rate related to the particular baud rate and (3) the derotator. The servos may have (1) first constants initially after a change in the station selection and (2) second time constants thereafter. The ADC gain is also servoed (1) initially in every ADC conversion and (2) subsequently in every nth ADC conversion where n=integer&#x3e;1. The above recover the QAM data without any of the coaxial cable noise or distortions.

System for, and method of, processing quadrature amplitude modulated signals

Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Multi-pair gigabit ethernet transceiver

Compensating for noise in a wireless communication system

Methods to compensate for noise in a wireless communication system

Multi-pair gigabit Ethernet transceiver

Multi-pair gigabit ethernet transceiver having a single-state decision feedback equalizer

Growing community of inventors

San Juan Capistrano, CA, United States of America

Henry Samueli