Nvidia Corporation

Silicon Graphics, Incorporated

Mips Technologies, Inc.

Microsoft Technology Licensing, LLC

Nvida Corporation

Nividia Corporation

Silicon Grpahics, Inc.

Henry Packard Moreton

Yury Y Uralsky

Eric Brian Lum

John Erik Lindholm

Jerome Francis Duluk, Jr

Ziyad Sami Hakura

Matthew Nicholas Papakipos

Timothy J Van Hook

Justin S Legakis

William A Huffman

Earl A Killian

Harold Robert Feldman Zatz

John Stephen Montrym

Andrew J Tao

Rui Manuel Bastos

Cass Watson Everitt

Simon S Moy

Peter Y Hsu

Douglas H Rogers

Dominic Acocella

Emmett Michael Kilgariff

David B Kirk

Vimal S Parikh

Kayvon Fatahalian

Eric Enderton

Christoph Kubisch

Dale L Kirkland

Jeffrey A Bolz

Patrick Richard Brown

Steven James Heinrich

Marco Salvi

Tyson J Bergland

Walter Robert Steiner

Jonathan J Dunaisky

Michael L Fuccio

Steven E Molnar

Alexander Lev Minkin

Andrew D Bowen

Jesse David Hall

Craig Michael Wittenbrink

Pierre Boudier

Thomas H Kong

Shirish C Gadre

Mark J Kilgard

John R Nickolls

Brian K Langendorf

John Matthew Burgess

Carroll Philip Gossett

David G Reed

David Conrad Tannenbaum

Gregory Muthler

Magnus Andersson

Aaron Eliot Lefohn

Michael Brian Cox

Michael Alan Fetterman

Anjul Patney

Roger L Allen

Alexey Panteleev

Christopher Ryan Wyman

Stefano A Pescador

Evgeny Makarov

Christopher James Goodman

Matthew N Papakipos

Justin Cobb

Cyril Crassin

Sergey Bolotov

Brett Coon

Stuart F Oberman

Timo Oskari Aila

Jonah Matthew Alben

Tero Tapani Karras

Walter E Donovan

John H Edmondson

Ming Yiu Siu

James Leroy Deming

Abraham Benjamin De Waal

Te-Li Lau

Douglas A Voorhies

Brian Matthew Fahs

Bengt-Olaf Schneider

Paolo Enrique Sabella

Hassane S Azar

Bryon S Nordquist

Eric T Anderson

Rui Bastos

Franklin C Crow

Robert Steven Glanville

Daniel P Wilde

Mark J French

Duncan Andrew Riach

Lars Nyland

Bryan E Loucks

Lordson L Yue

Christian Amsinck

Ian Buck

Yan Yan Tang

Poornachandra Rao

Jayant B Kolhe

Bent Hagemark

Richard Craig Johnson

A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.

Displaced micro-meshes for ray and path tracing

The present technology augments the GPU compute model to provide system-provided data marshalling characteristics of graphics pipelining to increase efficiency and reduce overhead. A simple scheduling model based on scalar counters (e.g., semaphores) abstract the availability of hardware resources. Resource releases can be done programmatically, and a system scheduler only needs to track the states of such counters/semaphores to make work launch decisions. Semantics of the counters/semaphores are defined by an application, which can use the counters/semaphores to represent the availability of free space in a memory buffer, the amount of cache pressure induced by the data flow in the network, or the presence of work items to be processed.

Programming model for resource-constrained scheduling

One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.

Adaptive shading in a graphics processing pipeline

In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images. In operation, the parallel processor causes execution threads to execute a task shading program on an input mesh to generate a task shader output specifying a mesh shader count. The parallel processor then generates mesh shader identifiers, where the total number of the mesh shader identifiers equals the mesh shader count. For each mesh shader identifier, the parallel processor invokes a mesh shader based on the mesh shader identifier and the task shader output to generate geometry associated with the mesh shader identifier. Subsequently, the parallel processor performs operations on the geometries associated with the mesh shader identifiers to generate a rendered image. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.

Techniques for representing and processing geometry within an expanded graphics processing pipeline

In various embodiments, a deduplication application pre-processes index buffers for a graphics processing pipeline that generates rendered images via a shading program. In operation, the deduplication application causes execution threads to identify a set of unique vertices specified in an index buffer based on an instruction. The deduplication application then generates a vertex buffer and an indirect index buffer based on the set of unique vertices. The vertex buffer and the indirect index buffer are associated with a portion of an input mesh. The graphics processing pipeline then renders a first frame and a second frame based on the vertex buffer, the indirect index buffer, and the shading program. Advantageously, the graphics processing pipeline may re-use the vertex buffer and indirect index buffer until the topology of the input mesh changes.

Techniques for pre-processing index buffers for a graphics processing pipeline

A graphics processing pipeline includes three architectural features that allow a fragment shader to efficiently calculate per-sample attribute values using barycentric coordinates and per-vertex attributes. The first feature is barycentric coordinate injection to provide barycentric coordinates to the fragment shader. The second feature is an attribute qualifier that allows an attribute of a graphics primitive to be processed without conventional fixed-function interpolation. The third feature is a direct access path from the fragment shader to triangle data storage hardware resources where vertex attribute data and/or plane equation coefficients are stored. Allowing the fragment shader to calculate per-sample attribute values in this way advantageously increases system flexibility while reducing workload associated with triangle plane equation setup.

System-generated stable barycentric coordinates and direct plane equation access

Methods and apparatuses are disclosed for reporting texture footprint information. A texture footprint identifies the portion of a texture that will be utilized in rendering a pixel in a scene. The disclosed methods and apparatuses advantageously improve system efficiency in decoupled shading systems by first identifying which texels in a given texture map are needed for subsequently rendering a scene. Therefore, the number of texels that are generated and stored may be reduced to include the identified texels. Texels that are not identified need not be rendered and/or stored.

Method and apparatus for obtaining sampled positions of texturing operations

In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images via a shading program. In operation, the parallel processor causes a first set of execution threads to execute the shading program on a first portion of the input mesh to generate first geometry stored in an on-chip memory. The parallel processor also causes a second set of execution threads to execute the mesh shading program on a second portion of the input mesh to generate second geometry stored in the on-chip memory. Subsequently, the parallel processor reads the first geometry and the second geometry from the on-chip memory, and performs operations on the first geometry and the second geometry to generate a rendered image derived from the input mesh. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.

Techniques for representing and processing geometry within a graphics processing pipeline

One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques.

Rendering to multi-resolution hierarchies

A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.

Hardware for parallel command list generation

A system, method, and computer program product are provided for rendering at variable sampling rates. Vertex coordinates for 3D primitive are received from a shader execution unit, and an arithmetic operation is performed on the vertex coordinates by fixed operation circuitry to produce modified vertex coordinates in homogeneous coordinate space. The modified vertex coordinates are transformed from homogeneous coordinate space into screen-space to produce screen-space vertex coordinates of a transformed 3D primitive and the transformed 3D primitive is rasterized in screen-space using the screen-space vertex coordinates to produce an image for display.

System, method, and computer program product for rendering at variable sampling rates using projective geometric distortion

A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports.

System, method, and computer program product for executing processes involving at least one primitive in a graphics processor, utilizing a data structure

Growing community of inventors

Woodside, CA, United States of America

Henry Packard Moreton