Pericom Semiconductor Corporation

Network Excellence for Enterprises Corp.

Henry P Ngai

Michael Yimin Zhang

A Pseudo-Ethernet switch has a routing table that uses Ethernet media-access controller (MAC) addresses to route Ethernet packets through a switch fabric between an input port and an output port. However, the input port and output port have Peripheral Component Interconnect Express (PCIE) interfaces that read and write PCI-Express packets to and from host-processor memories. When used in a blade system, host processor boards have PCIE physical links that connect to the PCIE ports on the Pseudo-Ethernet switch. The Pseudo-Ethernet switch does not have Ethernet MAC and Ethernet physical layers, saving considerable hardware. The switch fabric can be a cross-bar switch or can be a shared memory that stores Ethernet packet data embedded in the PCIE packets. Write and read pointers for a buffer storing an Ethernet packet in the shared memory can be passed from input to output port to perform packet switching.

Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports

A network connection is transparently shared among two or more processors. A shared network interface controller (NIC) has two or more sets of context registers that may include Ethernet command and pointer registers. Each set of context registers is accessed by a different processor. The processors are separated from the shared NIC by an Advanced Switching (AS) network. AS packets to write the context registers are embedded in AS packets that contain turnpool information that specifies a route through the AS network. Turnpools for AS packets from the different processors are unique and used to indicate which set of context registers to access. Each turnpool-identified context is assigned a different external network (Ethernet) address. External packets received by the shared NIC from the external network are sent inside AS packets over the AS network to the correct processor by associating the packet's external network address with a turnpool-context.

Shared network-interface controller (NIC) using advanced switching (AS) turn-pool routing field to select from among multiple contexts for multiple processors

An adjustable-delay filter performs wave shaping to emulate pre-emphasis or de-emphasis of transmission-line signals. The adjustable-delay filter uses analog components and does not need a clock. The receiver does not have to recover a bit-clock from the data stream, eliminating a clock recovery circuit. An input buffer receives the input signal and drives current to a summer and to an adjustable delay. The adjustable delay inverts and delays the current and drives a delayed, inverted current to the summer. The summer combines the delayed, inverted current and the current from the input buffer to generate an output signal. The delay time of the adjustable delay can be programmed by a user and is less than the bit period. After a signal transition, the output signal initially spikes higher, then falls back to a nominal level after the delay time has expired. The initial signal spike emulates de-emphasis or pre-emphasis.

Pre-emphasis and de-emphasis emulation and wave shaping using a programmable delay without using a clock

Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. Some lanes are directly connected from the root complex host to each slot. Each slot is driven by a different port and a different direct physical layer on the host. Other lanes are configurable and can be driven by any port and use a configurable physical layer on the host. These configurable lanes pass through an external switch or crossbar that connects the lanes from the host to one or more of the slots. The direct-connect lanes can be the first lanes to a slot while the configurable lanes are the higher-numbered lanes.

Optimized topographies for dynamic allocation of PCI express lanes using differential muxes to additional lanes to a host

An enhanced Peripheral Component Interconnect Express (PCIe) switch eliminates or reduces head-of-line blocking for memory reads initiated by peripheral endpoint devices. A memory-read request packet from a first peripheral endpoint device is intercepted by the enhanced PCIe switch, which generates a series of substitute request packets to the root complex and memory. The same requestor ID is used in all packets, but the original tag is replaced with a sequence of substitute tags in the substitute packets. The switch receives a sequence of reply packets with memory-read data, replaces substitute tags with original tags, and sends the reply packets to the peripheral endpoint device. Substitute request packets for different peripheral endpoint devices are alternately sent from the switch to the root complex to prevent head-of-line blocking by one peripheral endpoint device. The amount of data in each substitute request packet is smaller than the original requests to reduce blocking latencies.

Flow-splitting and buffering PCI express switch to reduce head-of-line blocking

Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. The host has 2primary lanes plus one extra lane. The extra lane is allocated to a slot when another slot uses all 2primary lanes. The extra lane ensures that a low-priority peripheral has at least one lane when a high-priority peripheral requires all primary lanes. A partial cross-bar switching matrix between the host and peripheral slots switches lanes at the physical layer using transistor bus switches. A switch controller can be programmed by configuration software to enable transistor bus switches to allocate and connect host lanes to slot lanes. Peripherals can have 1, 2, 4, 8, 12, or 16 lanes allocated and may be inserted into any of the slots.

Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host

A network switch routes switch packets among nodes with input and output ports. The nodes are connected together in a loop by two buses. One bus sends packets in a clockwise direction around the loop of nodes, while the other bus sends packets in a counter-clockwise direction around the loop. Each bus is divided into links between adjacent nodes, which examine and forward the packets to the next node in the loop. A packet is duplicated and injected onto both buses from a source node, reaching half of the nodes in one direction, and the other nodes in the opposite direction. A distance value in the packet header is set to half of the number of nodes so that the packet is removed after traveling half-way around the loop. A bit-mask in the header indicates nodes to receive the packet, or source-monitoring can remove packets half-way around the loop.

Dual-loop bus-based network switch using distance-value or bit-mask

A hybrid data parallel/serial data transfer system with phase adjustment and symbol coding for switching digital data packets in order to facilitate massive high speed, high capacity transfer of information with a limited number of signal lines. The transfer of information is processed over cross-bar networks. Much higher data transfer speed is possible than in a conventional serial data transfer. Moreover, the bits or Tera bits can be transferred easily over long distances. Data is transmitted over a communication link or trunk consisting of one of more cross-bar networks. Each message is transmitted as a sequence of groups of data bits, the bits in each group are transmitted in parallel over the trunk wherein each line or path carries a signal and each message is preceded by a serial start pattern. The receiver comprises a plurality of decoders for receiving data signals from the trunk. The arrangement overcomes the problem of data skew due to different transmission times over the lines of the trunk.

Data switching system with cross bar transmission

A hybrid data parallel/serial data transfer system with phase adjustment and symbol coding for switching digital data packets in order to facilitate massive high speed transfer of information with a limited number of signal lines. Much higher data transfer is possible than in a conventional serial data transfer. Multi-giga bits or Tera bits can be transferred easily over a long distance using this invention. Data transmission apparatus is described in which data is transmitted over a communication link or trunk consisting of a plurality of lines. Each message is transmitted as a sequence of groups of data bits, the bits in each group being transmitted in parallel over the trunk. Each line or path carries a signal and each message is preceded by a serial start pattern. The receiver comprises a plurality of decoders for receiving data signals from the trunk. These signals are fed to a separate buffer. The contents of the buffer are then read out in parallel. The arrangement overcomes the problem of data skew due to different transmission times over the lines of the trunk.

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Coto de Caza, CA, United States of America

Henry P Ngai