Texas Instruments Corporation

Other

Henry M Darley

Theodore Warren Houston

Jeffrey A Niehaus

Michael C Gill

Al F Tasch, Jr

James Bernard Kruger

Edison H Chiu

Maria B Hipona

Chauncey L Everett

Horng S Fu

Kevin M Ovens

Donald Edward Steiss

Dale C Earl

Dinh T Ngo

Han T Yuan

Jim Dodrill

Paul C Wang

A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

Circuitry for transferring data from a data bus and temporary register

A rounding circuit (10) for converting and rounding an M bit output from an adder array (12) into a N bit binary magnitude representation includes an incrementer (18) which increments the output of the adder array (12) prior to conversion. A borrow calculator (16) generates a select signal to a multiplexer indicating whether covnersion of the M bit number requires a borrow from the upper N bits. The select signal is used to choose between the incremented or non-incremented output. A converter/decrementer (22) converts the selected output of the multiplexer (20) into a binary magnitude number and also computes the magnitude representation decremented by one. A rounding circuitry (24) computes the rounding direction based on a control signal from control circuitry (26). The rounder circuit (10) calculates rounding information for two cases: (a) assuming that no normalization of the converted value is necessary and (b) assuming that normalization of the converted value is necessary. A selector/shifter (28) chooses between the decremented and non-decremented values based on the rounding information.

Method and apparatus for rounding in high-speed multipliers

A multiplying circuit (10) receives a multiplicand A and multiplies it by multiplier B. An Octal recoder (18) recodes the multiplier B into octal digits having a value from 4 to -4. A tripling generator determines the product of three times the multipicand. Partial product generators (22a-h) connected to the Octal recoder multiplex between the multiplicand A and the 3*A product, and include shifter and inverter circuitry to generate the partial products. Signed digit adders (24a-d, 26a-b and 28) add the partial products.

High speed multiplier

Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

High speed numerical processor for performing a plurality of numeric

A signed digit adder (10) includes a plurality of cells (12) which input signals X.sub.s, X.sub.m, Y.sub.s, Y.sub.m, R.sub.-1 and U.sub.-1, where X.sub.s and X.sub.m are the sign and magnitude bits of one digit of a signed bit representation. Similarly, Y.sub.s and Y.sub.m are the sign and magnitude bits of the second operand. R.sub.-1 and U.sub.-1 are signals received from the preceding cell (12). Each cell outputs R and U bits, and the sum bits Z.sub.s and Z.sub.m. Each cell (12) comprises function blocks (14-26) which determine the outputs from the given inputs. Function block (14) determines the output R as NOT (X.sub.s +Y.sub.s). Function block (20) determines the output U=E.NOT (R.sub.-1)+NOT (E) . NOT (Q) where Q=(NOT (X.sub.s))+NOT (Y.sub.s).X.sub.m. The determination of Q is performed in function block (16). Function block ( 24) determines the output Z.sub.s =U.sub.-1.T and function block (26) determines the output Zm=U.sub.-1 XOR(NOT(T)). T is determined in function block (22)=E XOR (NOT (R.sub.-1)). E is determined in function block (18) as X.sub.m XOR Y.sub.m. Function blocks (14-26) are optimized for speed relative to the temporal validity of the inputs.

Signed digit adder circuit

Floating point processor architecture

A signed digit adder (10) includes a plurality of cells (12) which input signals X.sub.s, X.sub.m, Y.sub.s, Y.sub.m, R.sub.-1 and U.sub.-1, where X.sub.s and X.sub.m are the sign and magnitude bits of one digit of a signed bit representation. Similarly, Y.sub.s and Y.sub.m are the sign and magnitude bits of the second operand. R.sub.-1 and U.sub.-1 are signals received from the preceding cell (12). Each cell outputs R and U bits, and the sum bits Z.sub.s and Z.sub.m. Each cell (12) comprises function blocks (14-26) which determine the outputs from the given inputs. Function block (14) determines the output R as NOT(X.sub.s +Y.sub.s). Function block (20) determines the output U=E.multidot.NOT(R.sub.-1)+NOT(E).multidot.NOT(Q) where Q=(NOT (X.sub.s)+NOT (Y.sub.s)).multidot.X.sub.m. The determination of Q is performed in function block (16). Function block (24) determines the output Z.sub.s =U.sub.-1 .multidot.T and function block (26) determines the output Z.sub.m =U.sub.-1 XOR (NOT (T)). T is determined in function block (22)=E XOR (NOT (R.sub.-1)). E is determined in function block (18) as X.sub.m XOR Y.sub.m. Function blocks (14-26) are optimized for speed relative to the temporal validity of the inputs.

A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output form the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessry to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.

Floating point/integer processor with divide and square root functions

A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is selfaligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

Self-aligned gate method for making MESFET semiconductor

A noninverting amplifier circuit for one propagation delay complex logic gates. The noninverting amplifier circuit is compatible with field effect transistor logic, including depletion-mode Schottky barrier field effect transistor (MESFET) inverting logic, gates. The basic noninverting amplifier circuit, utilizes field effect transistors (FET) and diodes, and comprises input interface means for receiving an input voltage signal, amplifier means for providing noninverted amplification of the input voltage signal, and buffer means for driving, and shifting the voltage level of the amplified input voltage signal. In another embodiment, additional circuit means for enabling performance of the 'AND' logic function is included in the basic noninverting amplifier circuit. In a third embodiment, additional circuit means for enabling performance of the 'OR' logic function is included in the basic noninverting amplifier circuit. The input and output voltages of the various embodiments which utilize the noninverting amplifier logic circuit are compatible with those of inverting logic circuits. Some examples of higher level complex one propagation delay logic gates which utilize the circuit in combination with inverting logic circuitry are also illustrated.

Noninverting amplifier circuit for one propagation delay complex logic

A static-type noninverting memory cell for one propagation delay memory circuits which is compatible with inverting and noninverting field effect transistor logic, such as, for example, depletion mode Schottky barrier field effect transistor (MESFET) inverting logic. The basic memory cell utilizes field effect transistors and a diode, and comprises an input for receiving an input signal, a transistor operating in a switching mode and connected to the input for registering the logic state of the input signal, a memory section which includes a pair of transistors each of whose respective gates are connected to the sources, a diode interposed therebetween, and a logic state-holding transistor for retaining a stored logic state of the registered input signal, and an output terminal connected between the diode and one of the transistor pair of the memory section from which the stored logic state within the memory section may be sensed. In one embodiment, the basic memory cell is combined with noninverting logic gates to provide a one propagation delay D type flip-flop memory circuit. In another embodiment, the basic memory cell is combined with noninverting logic gates to provide a one propagation delay D bar type flip-flop memory circuit. The input and output voltages of the various embodiments of the subject invention are compatible with those of inverting and noninverting logic circuits.

Static noninverting memory cell for one propagation delay memory circuits

An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath a thick field oxide, depletion and enhancement mode device channel implants, implanted source and drain regions, selective oxidation to form self-aligned gates, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.

Method of making an improved MESFET semiconductor device

MESFET devices are fabricated on a semiconductor substrate using a LOCOS (localized oxidation of silicon) process twice during the fabrication. The first LOCOS process provides device separation with a self-aligned thick-field oxide (SATO). The second LOCOS provides separation of gate and source/drain regions for each device, and self-aligns the gate contact with the channel implant. Devices fabricated by this method exhibit reduced series resistance, and improved metal step coverage.

Method for fabricating MESFET device using a double LOCOS process

A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

A MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a method which consists of an implanted channel stopper underneath a thick field oxide, implanted source and drain regions, depletion and enhancement mode device channel implants, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.

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Plano, TX, United States of America

Henry M Darley