Texas Instruments Corporation

Henry Litzmann Edwards

Binghua Hu

Akram Ali Salman

Tathagata Chatterjee

James Robert Todd

Xiaoju Wu

Sameer P Pendharkar

Jeffrey R Debord

Md Iqbal Mahmud

Alexei Sadovnikov

Dimitar Trifonov

Joseph Maurice Khayat

Kenneth James Maggio

Toan Tran

Lili Yu

Debarshi Basu

Christopher Boguslaw Kocon

Ricky A Jackson

Robert Allan Neidorff

Abbas Ali

Robert Christopher Bowen

Greg Charles Baldwin

Andrew Derek Strachan

Lance Stanford Robertson

Martin B Mollat

Marco A Gardner

James Becker

Barry Jon Male

Archana Venugopal

Rahmi Hezar

John Lin

Joe R Trogolo

Orlando Lazaro

Yongxi Zhang

Ashesh Parikh

Bradley David Sucher

Jonathan Philip Davis

Jihong Chen

Vladimir Bolkhovsky

John Christopher Shriner

Shariq Arshad

Andres Arturo Blanco

Christopher Scott Whitesell

Robert M Higgins

Li Wang

Richard B Irwin

Stephanie Leanne Hilbun

Stephen Isaac Brink

Wei Da

Chris Bowen

Howard S Lee

Curry Bachman Taylor

Mohamed Kamel Mahmoud

Robert James Todd

Baher S Haroun

Srinath Mathur Ramaswamy

Mahalingam Nandakumar

Taylor R Efland

William Robert Krenik

Leland Scott Swanson

Glen D Wilk

Theodore Sidney Moise

Thomas M Moore

Hideaki Kawahara

Gerd Schuppener

Shyh-Horng Yang

Hisashi Shichijo

John P Erdeljac

Angelo William Pereira

Jarvis Benjamin Jacobs

Ankur Chauhan

Gangqiang Zhang

Ayman A Fayed

Kushal D Murthy

Leif Christian Olsen

Neeraj P Nayak

Gabriel J Gomez

Sameer P Pendharker

Jeffrey L Large

Kaiyuan Chen

Oguz Altun

Robert C Bowen, Jr

Miaad Aliroteh

Sung-Jen Fang

Narayana Sateesh Pillai

Dhanoop Varghese

Chris Barr

Clint Alan Naquin

Udumbara Wijesinghe

Josh Du

Britton Robbins

Patrick Cruise

Kah Mun Low

Vladimir N Bolkhovsky

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter.

LOCOS fillet for drain reduced breakdown in high voltage transistors

A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.

System for determining leakage current of a field effect transistor over temperature

An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

High voltage avalanche diode for active clamp drivers

An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.

Reducing transistor breakdown in a power FET current sense stack

A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

Transistor device with buffered drain

An integrated circuit includes a semiconductor substrate with a semiconductor surface layer having a first conductivity type and a top surface, a diode including a buried region within the surface layer, the buried region having an opposite second conductivity type and being spaced apart from the top surface by a portion of the semiconductor surface layer having the first conductivity type, a dielectric layer over the surface layer, and a metal layer located over the dielectric layer and including an aperture extending laterally in a first direction over the semiconductor surface layer and laterally spaced apart from the buried region in a second direction.

Wide angle optical angle sensor

A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Control of locos structure thickness without a mask

A switching regulator includes a low-side switching transistor, a snubber transistor, a first pull-down transistor, and a second pull-down transistor. The low-side switching transistor includes a first current terminal and a second current terminal. The first current terminal is coupled to a switching node. The second current terminal is coupled to a ground terminal. The snubber transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to the switching node. The second current terminal is coupled to the ground terminal. The first pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal. The second pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal.

Switching regulator with configurable snubber

A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

Rugged LDMOS with field plate

A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure in a silicon recess on the silicon portion of the hybrid device. The silicon recess contains a silicon recess nitride sidewall. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon.

Hybrid component with silicon and wide bandgap semiconductor material in silicon recess with nitride spacer

A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon.

Hybrid component with silicon and wide bandgap semconductor material

An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Isolation structure for IC with epi regions sharing the same tank

The present disclosure introduces integrated circuits and related manufacturing methods, wherein each integrated circuit includes an electronic device and a thermoelectric circuit. The electronic device is formed in and/or over a semiconductor substrate. The thermoelectric circuit includes thermopiles formed in and/or over the semiconductor substrate and electrically connected in series. The thermoelectric circuit is configured to modulate operation of the electronic device in response to a potential produced by the plurality of thermopiles.

Power transistor thermal control via integrated thermoelectric device

A nanoscale thermoelectric device, which may be operated as a refrigerator or as a thermoelectric generator includes N-type and p-type active areas connected to a central terminal and end electrodes made of interconnect metal. Reducing lateral dimensions of the active areas reduces vertical thermal conduction, thus improving the efficiency of the thermoelectric device. The thermoelectric device may be integrated into the fabrication process sequence of an IC without adding process cost or complexity. Operated as a refrigerator, the central terminal may be configured to cool a selected component in the IC, such as a transistor. Operated as a thermoelectric generator with a heat source applied to the central terminal, the end terminals may provide power to a circuit in the IC.

Nanoscale thermoelectric refrigerator

A sensor chip includes a sensor pixel. The sensor pixel includes an avalanche photodetector. A circuit is adjacent to the avalanche photodetector. The circuit is coupled to the avalanche photodetector. An isolation structure at least partially encloses the circuit and is between the avalanche photodetector and the circuit.

Photodiode integrated with circuit

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Garland, TX, United States of America

Henry Litzmann Edwards