Taiwan Semiconductor Manufacturing Comp. Ltd.

Henry Lin

Yi-Lin Chuang

Yin-An Chen

Amos Hong

Szu-Ju Huang

Szu-ju Huang

Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Rule check violation prediction systems and methods

Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

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Hsinchu, Taiwan

Henry Lin