Lattice Semiconductor Corporation

Advanced Micro Devices Corporation

Henry Law

Fabiano Fontana

Om P Agrawal

Howard H Tang

David Lee Rutledge

Bai Yen Nguyen

Brad Sharpe-Geisler

Giap H Tran

Jack Tim Wong

Kiet Truong

In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

Flexible memory architectures for programmable logic devices

A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supply operable to provide power to the logic core of the PLD, such as the programmable logic blocks, routing structure, and volatile configuration memory. The internal power supply powers down the logic core in response to assertion of a power-down signal, while power is maintained to other circuitry of the PLD.

Programmable logic device with power-saving architecture

Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.

Programmable logic devices with user non-volatile memory

Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic blocks and the input/output blocks. A first non-volatile memory may store user information, besides configuration data, and a first port includes a dedicated serial peripheral interface to provide access to the first non-volatile memory.

Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.

Programmable logic devices with transparent field reconfiguration

A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

An output buffer circuit is disclosed that minimizes propagation delay and crowbar current. This circuit receives a data input signal and provides an output signal. This circuit includes a pull-up transistor, a first pull-down transistor, a speed improvement circuit and a crowbar current reduction circuit. The speed improvement circuit comprises an inverter with small propagation delay coupled to a second pull-down transistor which is smaller than the first pull-down transistor. The speed improvement circuit minimizes the propagation delay of the circuit when the data input signals changes from a high logic level to a low logic level by speeding up the initial rate of fall of the output signal due to the fast turning on of the second small pull-down transistor which receives the data input signal quickly through the small-propagation-delay inverter. The crowbar current reduction circuit comprises a first crowbar current reduction transistor which is smaller than the pull-up transistor. The crowbar current reduction circuit minimizes the crowbar current through the pull-up transistor and the first pull-down transistor when the data input signals changes from a high logic level to a low logic level by speeding up the turning off of the pull-up transistor due to the fast turning on of the small first crowbar current reduction transistor which receives the data input signal quickly through the small-propagation-delay inverter. A split Ground metal bus and a split package lead are used for minimizing noise.

High speed CMOS output buffer circuit minimizes propagation delay and

A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level. The several embodiments disclosed provide: 1) a high speed NOR gate that offers high speed performance on both the low-to-high and high-to-low transitions; 2) a high speed NOR gate for which voltage swings on the input circuits thereof are minimal; 3) a high speed NOR gate with pull-up current temperature and voltage compensation for improved performance on the low-to-high transition of the output; and 4) a high speed NOR gate using a feedback technique to regulate and limit the logic low voltage on the output such that this level has minimal variation independent of the number of the NOR inputs held in the logic high state.

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Los Altos, CA, United States of America

Henry Law