Racal-milgo Limited

Racal Data Communications Inc.

Henry H Parrish

Philip F Kromer, Iii

Ran F Chiu

Ming L Kao

Rangarajan Srinivasagopalan

Laurence F Turner

John W Bailey

To enable binary data to be differentially encoded into symbols (waves) for transmission the data is applied in n-bit data-words to produce symbols which, when displayed in a phasor-diagram, are in three groups in three 120.degree.-phase-sectors respectively, the number and dispositions of the symbols in the three sectors being the same. The encoding is such that, depending upon the data-word to be transmitted the sector in which a symbol is produced is rotated by 0.degree., 120.degree. or 240.degree. relative to the next preceding sector containing a symbol. In some embodiments one of the 2.sup.n possible different data-words is applied to produce an absolute symbol of zero amplitude. At a receiver the received symbols are decoded having regard to the 0.degree., 120.degree. and 240.degree. differential sector-rotations.

Differential encoder and decoder for transmitting binary data

An automatic adaptive equalizer operative on a test pattern including a carrier-only period, clock-only period and a single test impulse. The equalizer employs a transversal filter under control of a microprocessor. Samples of in-phase and quadrature phase components of the received impulse response are cross correlated and autocorrelated to form elements of a complex matrix equation describing the optimum equalizer tap settings. The microprocessor performs a special interative operation utilizing elements of this equation to rapidly and exactly calculate the optimum initial settings for the tap constants. The clock-only portion of the test pattern is analyzed to accurately set a sampling clock to properly sample the received impulse so that matrix formation can be carried out within the duration of the received impulse. Initial equalization can be achieved in a time on the order of 30 milliseconds at a data rate of 9600 bits per second.

Fast learn digital adaptive equalizer

A digital transmitter wherein a read only memory (ROM) is addressed by subaddresses representing vector components of signal point positions of a desired transmit spectrum. In this manner, greatly reduced ROM storage requirements are achieved.

Digital transmitter with vector component addressing

Circuitry for detecting and correcting false equilibrium conditions generated in data modems by sudden changes in gain of an associated transmission system including a false gain detector which detects a low rate of production of symbols of largest magnitude and triggers a final gain circuit which initially jumps the overall system gain and thereafter adaptively adjusts the gain jump to the correct value.

Data modem false equilibrium circuit

A circuit for maintaining proper sampling timing in a data modem wherein main channel equalizer error is correlated with a derivative channel signal to drive a clock correction signal. The derivative channel signal is derived from an equalizer using fewer coefficients than required to derive the main channel equalized signal, and calculation of the equalized derivative and clock correction signal is performed only once every other Baud.

Sampling clock correction circuit

An automatic gain control circuit having a coarse analog gain adjustment section producing discrete increments of db gain and a fine digital gain adjustment section. The digital section provides for adjustment of gain through a final increment of db gain to achieve precise gain setting. The output of the digital section is squared and compared to a reference signal to derive an error signal whose value is fed to an apparatus which iteratively determines the precise coarse increment and fine digital settings to achieve the final desired gain setting.

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Miami Springs, FL, United States of America

Henry H Parrish