Chartered Semiconductor Manufacturing Ltd (corporation)

Henry Gerung

Yelehanka Ramachandramurthy Pradeep

Mei Sheng Zhou

Vijai Kumar Chhagan

Simon Yew-Meng Chooi

Jie Yu

Zheng Zou

Chivukula Subrahmanyam

Madhusudan Mukhopadhyay

Pei Ching Lee

Qinghua Zhong

Vijai Komar Chhagan

Jun Qian

Vijakomar Chhagan

Yelehanka Machandramurthy Pradee

Vijai Komar N Chhagan

A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; therein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

Method for forming an extended metal gate using a damascene process

A new method is provided for the integration of the of T-top gate process. Active regions are defined and bounded by STI's on the surface of a substrate. The pad oxide is removed from the substrate and replaced by a layer of SAC oxide. A thin layer of nitride is deposited that covers the surface of the created layer of SAC oxide and the surface of the STI regions. A layer of TEOS is deposited and etched defining the regions where the gate electrodes need to be formed. Gate spacers are next formed on the sidewalls of the openings that have been created in the layer of TEOS. The required implants (such as channel implant and threshold implant) are performed, the gate structure is then grown in the openings that have been created in the layer of TEOS. After the gate structure has been completed, the surface of the created structure is polished and the remaining layer of TEOS is removed. Source and drain regions implants can now be performed, LDD regions are implanted using a tilted implant. This tilted implant penetrates underneath the body of the created gate structures thereby creating the LDD regions. The removal of the layer of TEOS leaves in place the gate structures, one such structure is located in the active region of the surface of the substrate, two additional structures that have been created on the surface of the STI regions.

Self aligned T-top gate process integration

A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

A method for anisotropically etching a partially manufactured semiconductor structure, more specifically, a stacked FET gate structure containing a bottom anti-reflective coating (Barc) layer is described. The structure is covered with a photoresist layer which is patterned to defines the gate region. The processing chemistry is predominantly carbon tetrafluoride, (CF,) with the inclusion of chlorine (Cl,) where fluorine (F) is generated in the plasma as the etchant for the structure. During processing, the wafer is cooled with helium (He) that lowers the wafer temperature and promotes sidewall deposition from the fluorine species which acts as a passivation layer producing a anisotropic or vertical etch profile. The process reduces etch time and results in very repeatable end point control of the Bark etch and poly cap etch improving the control of the structure critical dimensions and improving process throughput. The reduction in the use of fluorine based species reduces any potential environmental impact.

Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon

A method to fabricate a floating gate with a sloping sidewall for a Flash Memory is described. Field oxide isolation regions are provided in the substrate. A silicon oxide layer is provided overlying the isolation regions and the substrate. A first polysilicon layer is deposited overlying the silicon oxide layer. A photoresist layer is deposited overlying the first polysilicon layer. The photoresist layer is etched to remove sections of the photoresist as defined by photolithographic process. The photoresist layer, the first polysilicon layer, and the silicon oxide layer are etched in areas uncovered by the photoresist layer to create structures with sloping sidewall edges. The photoresist layer is etched away. An interpoly dielectric layer is deposited overlying the structures, the sloping sidewall edges, and the isolation regions. A second polysilicon layer is deposited overlying the interpoly dielectric and the fabrication of the integrated circuit device is completed.

Method to fabricate a floating gate with a sloping sidewall for a flash memory

A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

Method to reduce trench cone formation in the fabrication of shallow trench isolations

A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900&deg; C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.

Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer

A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer. The self-sealing oxide layer seals over the gaps between the silicon nitride thin layer and the silicon nitride liner layer to thereby form permanent air gaps between the adjacent metal interconnects, and the integrated circuit is completed.

Method to form self-sealing air gaps between metal interconnects

A method for fabricating a high-density high-capacity capacitor is described. A dielectric layer is provided overlying a semiconductor substrate. A sacrificial layer is deposited overlying the dielectric layer and patterned to form a pattern having a large surface area within a small area on the substrate. In one alternative, spacers are formed on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. A bottom capacitor plate layer is conformally deposited overlying the spacers. In a second alternative, a bottom capacitor plate layer is deposited overlying the patterned sacrificial layer and etched to leave spacers on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. In both alternatives, a capacitor dielectric layer is deposited overlying the bottom capacitor plate layer. A top capacitor plate layer is deposited overlying the capacitor dielectric layer and patterned to complete fabrication of a high-density high-capacity capacitor.

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Singapore, Singapore

Henry Gerung