USA As Represented by Secretary of the Navy

Henry D Ngo

Jia-Chi Samuel Chieh

Eric Noel Cartagena

Jener S Chang

A non-linear charge pump for phased lock loops. Furthermore, an auxiliary charge pump apparatus, comprising a positive switch electrically connected to a current source configured to supplement power to a charge pump, a negative switch electrically connected to a current sink configured to discharge power from the charge pump, a windowing comparator, further comprising an input signal received from a phase-locked loop, a first comparator configured to compare the input signal against a high voltage threshold, a second comparator configured to compare the input signal against a low voltage threshold, an AND logic gate configured to provide a window signal and an activation circuit electrically connected to the positive switch and negative switch. Additionally, a non-linear charge pump system and method for reacquiring frequency lock of a phase lock loop.

Non-linear charge pump for phased lock loops

An analog lock detector for a phase lock loop includes a detector, a logic gate, a delay circuit, and a guard gate inverter. The detector outputs up and down signals relating synthesized and reference frequencies. The logic gate outputs an initial lock signal combining the up and down signals. While the synthesized and reference frequencies are locked, the initial lock signal has a steady state except during brief intervals. The delay circuit outputs a delayed lock signal that time delays the initial lock signal by a delay amount, which matches a maximum allowed duration of the brief intervals while locked. A guard gate inverter outputs a final lock signal that combines the initial lock signal and the delayed lock signal. The final lock signal has the steady state indicating when the synthesized frequency is locked to the reference frequency, but without the brief intervals of deviation from the steady state.

Analog lock detector for a phase lock loop

A logic circuit for preventing false signals generated by radiation particle hits on sensitive nodes the circuit, comprising a first logic gate coupled to a third logic gate, a second logic gate coupled to the third logic gate, a multiplexer coupled to the third logic gate, an inverter coupled to the multiplexer, a pulldown transistor coupled to the first logic gate, and a latch coupled to the pulldown transistor. The first logic gate is coupled to the second logic gate, the pulldown transistor, and the latch. The second logic gate is coupled to the pulldown transistor and latch. The latch is coupled to the third logic gate and multiplexer. The multiplexer is coupled to the first logic gate and coupled to the second logic gate. The third logic gate outputs a high output signal only if both the first logic gate and second logic gate outputs the high output signal.

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Henry D Ngo