Macronix International Co., Ltd.

Alliedsignal Inc.

Honeywell International Inc.

Henry Chung

James Lin

Ching-Yu Chang

Ming-Chung Liang

Cheng-Chen Calvin Hsueh

Shi-Qing Wang

Tahorng Yang

Pei-Ren Jeng

Joseph T Kennedy

Chia-Chi Chung

Shin-Yi Tsai

Anna M George

Chung-Yeh Lee

An-Chi Wei

Kuo-Liang Wei

Jerry Lai

A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.

Method of reducing pattern pitch in integrated circuits

A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.

Method for fabricating read only memory including a first and second exposures to a photoresist layer

A method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution controls the defined pitches of the target layer by use of polymer spacer, photo-insensitive polymer plug and polymer mask during the process, so as to achieve the minimum pitch of the target layer beyond photolithographic resolution. Applied to memory manufacture, this method is capable of simultaneously overcoming the process difficulty of significant difference between polysilicon pitches in memory array region and periphery region.

Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution

A patterning method for fabricating integrated circuits. The method includes forming a material layer over a substrate and then forming a photoresist layer over the material layer. The photoresist layer has a thickness small enough to relax the limitations when the photoresist layer is patterned in a photolithographic process. A shroud liner is formed over the photoresist layer such that height of the shroud liner is significantly greater than width of the shroud liner. Thereafter, the shroud liner undergoes a processing treatment to remove the sections attached to the sidewalls of the photoresist layer. Using the remaining shroud liner as an etching mask, an etching operation is carried out to pattern the material layer.

Patterning method for fabricating integrated circuit

A method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method including providing a semiconductor substrate, forming a first layer over the semiconductor substrate, forming a second layer over the first layer, patterning the second layer to form a plurality of second layer patterns, patterning the first layer to form a plurality of first layer patterns, performing a tone reversal to form a reversed tone for the second layer patterns, and etching the first layer patterns using the reversed tone as a mask, wherein the etched first layer patterns have a final pitch size, and wherein the final pitch is smaller than the minimum pitch.

Fabrication method of sub-resolution pitch for integrated circuits

Dual damascene methods of fabricating conducting lines and vias in organic intermetal dielectric layers utilize sacrificial inorganic dielectrics. In one embodiment, a via opening formed in organic intermetal dielectric layers is filled with sacrificial inorganic dielectric. A line opening is formed aligned with the via opening. The sacrificial inorganic dielectric is selectively removed. The via and line openings are filled with conducting material. In a second embodiment, a line opening formed in organic intermetal dielectric layers is filled with sacrificial inorganic dielectric. A via opening is formed aligned with the line opening. The sacrificial inorganic dielectric is selectively removed. The via and line openings are filled with conducting material. The sacrificial inorganic dielectrics protect the organic intermetal dielectric layers, preserving critical dimensions and facilitating photoresist rework. The sacrificial inorganic dielectrics are removed without damaging the organic intermetal dielectric layers.

Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectrics

A method to relax the alignment accuracy requirement in an integrate circuit manufacturing is described. The method comprises forming a mask layer over a substrate, and the mask layer comprises a plurality of first openings. Thereafter, a buffer layer fills the first opening, followed by forming a photoresist layer over the substrate. The photoresist layer is then patterned to form a second opening that corresponds to the first opening, and the second opening exposes a portion of the buffer layer. Isotropic etching is then performed to remove the buffer layer exposed by the second opening to expose a sidewall of the first opening that corresponds to the second opening. The photoresist layer is further removed to expose the mask layer that comprises the embedded buffer layer and the opening pattern, which is used as a hard mask layer in a subsequent process.

&lsqb;Method to relax alignment accuracy requirement in fabrication for integrated circuit&rsqb;

A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features. The first and second polymer layers can be formed using dielectric resolution enhancement coating techniques.

Method for reducing pitch

The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics. An integrated circuit structure is formed having a substrate; an inorganic layer on the substrate which is composed of a pattern of metal lines on the substrate and an inorganic dielectric on the substrate between the metal lines; and an organic layer on the inorganic layer which is composed of an organic dielectric having metal filled vias therethrough which connect to the metal lines of the inorganic layer.

Integrated circuits with multiple low dielectric-constant inter-metal dielectrics

Method for fabricating read only memory including forming masking layers with openings and pre-coding the cell and peripheral regions

A method of manufacturing mask ROM is provided. A buried bit line is formed in a substrate and then a gate and a word line are formed over the substrate. Thereafter, a pre-coding layer with a plurality of pre-coding openings therein is formed over the substrate in a relatively high precision process. The pre-coding openings correspond in position to a plurality of coding regions on the substrate underneath the gate. A filler material is deposited into the pre-coding openings to form a filler layer. A coding mask having a plurality of coding openings is formed over the substrate in a relatively low precision process. The filler material inside the pre-coding openings that correspond in position to the code openings in the coding mask is removed. The coding mask is removed. Finally, a coding ion implant is carried out using the pre-coding layer and the filler layer as mask and hence ions are implanted into the code region through the pre-coding openings.

Coding method for mask ROM

A method for fabricating vias and trenches in a dual-damascene multilevel interconnection structure of an integration circuit is provided. The method uses chemical vapor deposition and flowfill dielectric technology to deposit a dielectric material at low temperature for fabricating interconnection structure in an integration circuit. It comprises the following steps: (a) forming photo-resist patterns; (b) depositing a dielectric layer at low temperature by chemical vapor deposition and flowfill dielectric technologies; (c) removing the dielectric layer by chemical-mechanical polishing to expose the photo-resist patterns; (d) removing the photo-resist patterns by chemical-mechanical polishing; and (e) stabilizing the dielectric layer by thermal curing.

Method for forming interconnection structure in an integration circuit

The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.

Fabrication of integrated circuits with borderless vias

A microelectronic device having a self aligned metal diffusion barrier is disclosed. A microelectronic device having a substrate and a dielectric layer on the substrate. A trench having inside walls is formed through the dielectric layer. A lining of a barrier metal is on the inside walls of the trench and a fill metal is in the trench between the linings on the inside walls of the trench. The fill metal and the barrier metal have substantially different removal selectivities. A covering of the barrier metal is on the fill metal and the covering spans the linings on the inside walls of the trench and conforms to the top of the fill metal in the trench.

Integrated having a self-aligned Cu diffusion barrier

The invention provides microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer and an additional layer of the first dielectric material positioned on the second dielectric material. At least one via extends through the first dielectric material layer and the second dielectric material layer, and at least one trench extends through the additional layer of the first dielectric material to the via. A lining of a barrier metal is formed on inside walls and a floor of the trench and on inside walls and a floor the via. A fill metal fills the trench and via in contact with the lining of the barrier metal.

Growing community of inventors

Taipei, Taiwan

Henry Chung