Newbridge Networks Corporation

Pmc-Sierra, Inc.

Alcatel Canada Inc.

Alcatel-Lucent Canada Inc.

Henry Chow

Mark William Janoska

Charles Mitchell

Michael Gassewitz

Steve Bews

Germain Bisson

Jim Ghadbane

Hossain Pezeshki-Esfahani

Albert D Heller

Anthony Hung

Srinivasan Ramaswamy

Jason Chen

A method and apparatus for line card redundancy in a communication switch is presented. The switch includes an arbiter coupled to the input of a switch core and a line card pair. The first line card of the line card pair is considered an active line card, whereas the second line card of the line card pair is considered the redundant, or inactive, line card. The active and inactive line cards are determined based on selection information received by the arbiter. Based on the selection information, the arbiter preferentially provides ingress data from the active line card to the corresponding input of the switch core. A router is coupled to the line card pair and to an output of the switch core. The router passes egress data from the switch core to at least one of the first and second line cards based on routing information included in the egress data.

Method and apparatus for line card redundancy in a communication switch

A data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank.

Transporting data transmission units of different sizes using segments of fixed sizes

Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size. Within each frame, the read addresses to be accessed by read memory operations can be rearranged to minimize memory bank access conflicts with either write addresses to be accessed by write memory operations or other read addresses.

Method of allowing random access to rambus DRAM for short burst of data

A method and apparatus for a high bandwidth multi-source interconnection using point-to-point buses that may be utilized in a communication switch is presented. In the communication switch, a number of output buffers are included to correspond to the outputs of the switch. Each output receives data from a number of different inputs to the switch. Each output buffer includes a plurality of queuing elements where each queuing element receives data from at least one of the inputs and buffers the data prior to insertion into an output data stream corresponding to the output of the output buffer. The plurality of queuing of elements are intercoupled in a daisy chain configuration such that a daisy chain output of one queuing element is coupled to the daisy chain input of the succeeding queuing element. The daisy chain configuration provides a data path through which a data stream that becomes the output of the output buffer is carried. A chain master queuing element at the head of the daisy chain inserts idles into the data stream unless an arbiter has instructed it to insert data that it has received from its corresponding inputs. Succeeding queuing elements on the daisy chain then receive the data stream and insert their data at the appropriate time determined by the arbitration grants received from the arbiter.

Method and apparatus for high bandwidth multi-source interconnection using point-to-point buses

The method for servicing queues holding messages, such as ATM data packets, for subsequent processing or transmission to a resource such as a communications link having a finite processing capability comprises the steps of servicing each queue by forwarding the messages thereof to the resource at time intervals corresponding to a guaranteed service rate of the queue, provided the queue is non-empty; and, during time intervals when none of the queues have messages being forwarded to the resource in conformance with the above step, servicing the queues in accordance with a proportion of a remaining or idle resource bandwidth allocated to each queue. The method is preferably carried out by a hierarchical scheduler comprising an exhaustive sub-scheduler servicing a plurality of lower level sub-schedulers in accordance with non-equal priority levels assigned thereto; M non-work conserving shaper sub-schedulers feeding the exhaustive sub-scheduler; and N work conserving idle bandwidth sub-schedulers feeding the exhaustive sub-scheduler. In such a scheduler, a queue concurrently contends for service by one of the shaper sub-schedulers and one of the idle bandwidth sub-schedulers, wherein the shaper sub-scheduler servicing the queue has a higher priority level with respect to the exhaustive sub-scheduler than the idle bandwidth sub-scheduler servicing the same queue. The technique distributes the idle bandwidth of the resource in a way which is de-coupled from the guaranteed service rates of the queues, thereby providing a more efficient bandwidth distribution.

Two-component bandwidth scheduler having application in multi-class digital communications systems

A communication system is provided for transmitting and receiving data cells containing control messaging and customer data, including a real-time development system (RDS) and means for generating a plurality of RDS events and RDS commands at predetermined locations within the communication system. Each of the RDS events having an event identifier and a variable length sequence of data bytes for defining the event. Each of the RDS commands having a command identifier and a variable length identifier for defining the command. The communication system also includes means for transmitting the RDS events and RDS commands as data cells throughout the communication system via identical communication links. The communication system also having means located throughout the communication system for selectively filtering the RDS events and RDS commands from the control messaging data and customer data. The communication system further includes means located throughout the communication system for displaying the RDS events which have been filtered for real-time diagnostics as well as means for supporting source and assembly level debug operations using the RDS commands and RDS events.

Communications system for receiving and transmitting data cells

A communication system is disclosed having a hub slot adapted to receive any one of a plurality of hub cards for receiving and transmitting data cells; a plurality of universal card slots; a plurality of interface cards insertable into any one of said plurality of universal card slots for receiving incoming ones of said data cells containing data and transmitting outgoing ones of said data cells containing data; an add bus having respective data links connected between individual ones of said universal card slots and said hub slot for receiving said outgoing ones of said data cells from said plurality of interface cards and transmitting said outgoing ones of said data cells to said hub slot; a drop bus having a single data link connected between all of said universal card slots and said hub slot for transmitting said incoming ones of said data cells from said hub slot to said plurality of interface cards; and means within each of said interface cards for filtering said incoming ones of said data cells from said drop bus and thereby routing said data cells to an appropriate one or more of said plurality of interface cards.

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Kanata, Canada

Henry Chow