International Business Machines Corporation

Henry Chin

George Totolos, Jr

Kevin W Kark

William Wu Shen

Christopher M Herring

John Edward Derrick

Kenneth Y Chan

Judy Shan-Shan Chen Johnson

Vesselina K Zaharinova-Papazova

A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

Dynamic sparing during normal computer system operation

Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when the counter accumulates a count exceeding a predetermined value.

Power governor for dynamic RAM

A method and apparatus for configuring a single point arbitration scheme for a commonly accessed communication bus using bus master devices with arbitration control circuitry included therein. Bus master devices including arbitration control circuitry may be connected to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same connections to the arbitration control bus provide signals which are decoded at each bus master device to provide a configuration status which indicates whether other bus master devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the arbitration. Accordingly, single point arbitration of a commonly accessed bus is configured without adding an external arbiter circuit to the bus system or otherwise increasing the I/O requirements of the bus master devices.

Configuration of a single point bus arbitration scheme using on-chip

A method and apparatus for configuring a centralized arbitration scheme for a commonly accessed communication bus using arbiter devices with arbitration control circuitry included therein. The arbiter devices, each of which is associated with a separate bus master device, include arbitration control circuitry and are coupled to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same arbiter device connections to the arbitration control bus provide signals which are decoded via arbitration configuration circuitry on each device to provide a configuration status indicating whether other devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the required arbitration. Moreover, the arbiter devices may include protocol translation logic for permitting the interconnection of bus master devices having different arbitration protocols than the protocol required for accessing the common bus.

Common arbiter interface device with arbitration configuration for

An apparatus and method are provided for maintaining lock characteristics while providing selective access to a cache during lock cycles. To guarantee that only one master accesses memory at a time, locked cycles are always passed to the internal arbitration unit of the memory controller, even if they are cache hits. If the local bus is not granted or cannot be guaranteed that it will be granted the bus for the locked cycle, the cycle is cancelled.

Bus protocol for locked cycle cache hit

A cache memory is provided which adjusts its response to addresses in accordance with the number of identical cache memory cards installed in the motherboard. Upon its installation in the motherboard a card is informed of its status as a master or a slave. As long as a slave is not installed the master responds to processor accesses over the entire address range of the computer. When a slave is installed a signal is sent to the master. Circuitry on the memory cards restricts the master response to half the address range. The slave being informed of its status restricts its response to the other half of the address range.

Cache address modification control

The cache controller of a second level cache in an Intel Pentium processor based computer system contains test circuitry that allows reading and writing directly into all tag RAM databit locations. This circuitry responds to a modified External Address Strobe (EADS#) command to invoke the tag test cycle. The EADS# command is normally used in a SNOOP read cycle by the system. In a SNOOP cycle, the main memory controller invokes the EADS# command to request the first level (L.sub.1) and second level (L.sub.2) caches for modified information stored in those caches. In the tag test cycle the EADS# command line is held down twice as long as it would in a normal SNOOP read Cycle. Because of its added length, the SNOOP cycle circuits in the L.sub.2 cache ignore the command on the EADS# command line. However, the tag RAM test circuitry in the L.sub.2 cache recognizes the extended EADS# strobe providing a path to access all bit locations in a tag RAM for both read and write cycles to test the tag RAM or to load those bit positions to selected states in testing other portions of the cache.

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Wappingers Falls, NY, United States of America

Henry Chin