Sandisk Technologies Inc.

Sandisk Corporation

Western Digital Technologies, Inc.

Sandick Technologies Inc.

Henry Chin

Nima Mokhlesi

Dana Lee

Dengtao Zhao

Wei Zhao

Vinod Robert Purayath

Deepanshu Dutta

Erika Penzo

James K Kai

George Matamis

Henry Chien

Takashi Whitney Orimoto

Han-Ping Chen

Gerrit Jan Hemink

Yingda Dong

Anubhav Khandelwal

Cynthia Hsu

Guirong Liang

Yuan Zhang

Lei Lin

Zhenming Zhou

James Fitzpatrick

Abhijeet Manohar

Richard David Barndt

Daniel Edward Tuers

Niranjay Ravindran

Hong-Yan Chen

Hua-Ling Cynthia Hsu

Deepak Raghu

Ravi J Kumar

Fanglin Zhang

Pitamber Shukla

Mostafa El Gamal

Tapan Samaddar

Zhuojie Li

Bernie Rub

Dong-Il Moon

Masaaki Higashitani

Johann Alsmeier

Xiang Yang

Jeffrey W Lutze

Liang Li

Tuan Duc Pham

Ching-Huang Lu

George Samachisa

Hiroyuki Kinoshita

Chris Avila

Shih-Chung Lee

Ashish Kumar Baraskar

Zhengyi Zhang

Donovan Lee

Xuan Tian

Atsushi Suyama

Ming Tian

Jian Feng Chen

Peter Rabkin

Jiahui Yuan

Huai-Yuan Tseng

Yu-Chung Lien

Ken Oowada

Gautam Ashok Dusija

Bo Lei

Changyuan Chen

Abhijith Prakash

Tai-Yuan Tseng

Sarath Chandran Puthenthermadam

Muhammad Masuduzzaman

Vinh Diep

Pao-Ling Koh

Yanjie Wang

Qing Li

Abu Naser Zainuddin

Parth Amin

Xiaoyu Yang

Joanna Lai

Yichao Huang

Arash Hazeghi

Abhilash Ravi Kashyap

Sateesh Desireddi

Jianzhi Wu

Jia Li

Toru Ishigaki

Shota Murai

Vincent Yin

Zelei Guo

Guanhua Yin

Jie Liu

Kyeongran Yoo

Yanwei He

LanLan Gu

Tony Zou

Dong-II Moon

Harshul Gupta

Ashwin D T

Ching Huang Lu

Shin-Chung Lee

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes each comprising a channel. The memory cells retain a threshold voltage and are operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is configured to apply a predetermined refresh read voltage to the word lines at predetermined intervals of time during a refresh read operation to maintain the memory cells in the second read condition. The control means also adjusts a read setup time in which the word lines are ramped up and the channel is discharged during a read operation based on occurrences of the refresh read operation.

Word line-dependent word line and channel read setup time in first read state of non-volatile memory

A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.

Systems and methods to avoid over programming at infrequent smart verify acquisition for high-performance 3D NAND

A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: during a program loop for programming a set of states, select a first bitline biasing mode that dictates a scheme for biasing a first set of bitlines and apply the first bitline biasing mode before verifying the set of states. The controller further configured to during another program loop for programming another set of states, select a second bitline biasing mode that dictates a scheme for biasing a second set of bitlines and apply the second bitline biasing mode before verifying the other set of states.

Hybrid precharge select scheme to save program ICC

Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.

Hybrid smart verify for QLC/TLC die

A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.

Memory programming techniques to reduce power consumption

The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.

Memory device with unique read and/or programming parameters

A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.

Programming of memory cells using a memory string dependent program voltage

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.

Read pass voltage dependent recovery voltage setting between program and program verify

The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

Techniques for checking vulnerability to cross-temperature read errors in a memory device

The memory device includes a plurality of dies, and each die includes a plurality of blocks with a plurality of word lines. Some of the word lines are arranged in a plurality of exclusive OR (XOR) sets with each XOR set containing word lines in the same positions across the plurality of dies. The memory device further includes a controller that is configured to program the word lines of the blocks of at least one of the dies in a first programming direction. The controller is further configured to program the word lines of the blocks of at least one other die in a second programming direction that is opposite of the first programming direction.

Mixing normal and reverse order programming in NAND memory devices

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.

Temperature-dependent word line voltage and discharge rate for refresh read of non-volatile memory

An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.

Time-tagging read levels of multiple wordlines for open block data retention

An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.

Word line zoned adaptive initial program voltage for non-volatile memory

Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

Digital temperature compensation filtering

Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

Reliability compensation for uneven NAND block degradation

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Fremont, CA, United States of America

Henry Chin