Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Henry Chen

Akira Ito

Liming Tsau

Surya Battacharya

Vincent Chen

Jay Shiau

Arya Behzad

Xiangdong Chen

Agnes Woo

Wei Xia

Jacob Jude Rael

Matthew Vernon Kaufmann

Guang-Jye Shiau

Malcolm MacIntosh

Ming Chen

Surya Bhattacharya

Yi Liu

Tzu-Hsin Huang

Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

FinFET devices

According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.

High voltage durability transistor and method for fabricating same

Forming a wafer level chip scale flip chip package includes determining isolation requirements of an integrated circuit formed in a semi conductive substrate from package signal connections of the wafer level chip scale flip chip package. Operation may further include, based upon the integrated circuit characteristics, selecting a thickness of at least one dielectric layer isolating a top metal layer of the integrated circuit from the package signal connections of the wafer level chip scale flip chip package, determining a minimum pitch of the package signal connections of the wafer level chip scale flip chip package, and determining a maximum lateral distance from the signal pad to a servicing package signal connection of the wafer level chip scale flip chip package and determining a position of the servicing package signal connection of the wafer level chip scale flip chip package based upon the maximum lateral distance.

Wafer-level flipchip package with IC circuit isolation

A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.

Low threshold voltage PMOS apparatus and method of fabricating the same

An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

Integrated fuse with regions of different doping within the fuse neck

A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second arm, and a via. The first arm has a first end and a second end. The second arm has a third end and a fourth end. The first arm and the second arm intersect and the first, second, third and fourth ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the first and second arms.

High density maze capacitor

A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a transverse arm, and a via. The upright arm has a top end and a bottom end that extend at substantially right angles to a central axis of the upright arm. The transverse arm has a left and right end that extend at substantially right angles to a central axis of the transverse arm. The upright arm and the transverse arm intersect to form a cross-like pattern and the top, bottom, left and right ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the upright and transverse arms.

High density metal-to-metal maze capacitor with optimized capacitance matching

A one-time programming memory element, capable of being manufactured in a 0.13 &#x3bc;m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

System and method for one-time programmed memory through direct-tunneling oxide breakdown

A one-time programming memory element, capable of being manufactured in a 0.13 &#x3bc;m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write circuit, having first and second switches coupled to the capacitor, and a read circuit also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write circuit to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

A one-time programming memory element, capable of being manufactured in a 0.13 &#x3bc;m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current, and a switch having a voltage tolerance higher than that of the capacitor/transistor, wherein the capacitor/transistor is one-time programmable as an anti-fuse by application of a voltage across the oxide layer via the switch to cause direct gate tunneling current to thereby rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

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Irvine, CA, United States of America

Henry Chen