Infineon Technologies Ag

Other

Qimonda Ag

Henry Bernhardt

Bernd Hintze

Frank Bernhardt

Thomas Hecht

Olaf Storbeck

Michael Stadtmueller

Christian Kapteyn

Michael Stadtmüller

Stefan Kainz

Thomas Seidemann

A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer

A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.

Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates

Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

Method for fabricating an integrated circuit on a semiconductor substrate

A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for low-pressure chemical vapor deposition or oxidation. A heating system is particularly useful for heating a reactor in which a plurality of wafers is held perpendicularly to the reactant gas flowing direction that is parallel to the longitudinal axis of the reactor, to enable a deposition or oxidation reaction. The heating system is adapted to change the reactor temperature during the process. In addition, a method heats a reactor to enable a reaction. Preferably, each of a plurality of reactor zones, into which the reactor is divided in a direction parallel to the reactant gas flowing direction, is heated at a different temperature profile indicating the temperature of this specific zone versus time. Thereby, the in-plane uniformity of deposited or oxidized layers can be largely improved.

Heating system, method for heating a deposition or oxidation reactor, and reactor including the heating system

Growing community of inventors

Dresden, Germany

Henry Bernhardt