Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Broadcom Corporation

Henry Arnold Park

Tamer Mohammed Ali

Afshin Momtaz

Namik Kocaman

Adesh Garg

Anand Jitendra Vasani

Ullas Singh

Ramy Awad

Mohammed Abdul-Latif

Shih-Hao Huang

Amr Amin Hafez Amin Abou-El-Sonoun

Huan-Sheng Chen

Chien-Hua Wu

Qaiser Nehal

Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state ('enabled') or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.

Wideband signal attenuator

A continuous time linear equalizer (CTLE) includes a first circuit path having a step response that increases from an first initial value to a steady state value higher than the first initial value. The CTLE also includes a second circuit path in parallel with the first circuit path, the second circuit path having a step response that increases from a second initial value to a peak and subsequently falls to second steady state value that is approximately equal to the second initial value. The CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.

Continuous time linear equalizer with a plurality of signal paths

Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.

Systems and methods for on-chip time-domain reflectometry

Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.

Circuits for delay mismatch compensation and related methods

System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.

Systems for reducing pattern-dependent inter-symbol interference and related methods

According to at least one aspect, a digital-to-analog converter (DAC) circuit configured to receive a digital signal and provide an analog signal is provided. The DAC circuit includes a first circuit configured to receive a first portion of the digital signal and generate a first output voltage at a level selected from a first plurality of levels where at least two adjacent voltage levels have a first potential difference. The DAC circuit further includes a second circuit configured to receive a second portion of the digital signal and generate a second output voltage at a level selected from a second plurality of levels where at least two adjacent voltage levels have a second potential difference and the second circuit includes a compensation circuit configured to adjust the second potential difference such that the second potential difference is an integer multiple of the first potential difference.

Digital to-analog converters with non-binary weighted cell array

A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

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San Jose, CA, United States of America

Henry Arnold Park