Xilinx, Inc.

Henry A Om'mani

Thomas James Davies

Described is a power multiplexer that alternately transmits zero, supply voltage, and a relatively high voltage to a common output node. The power multiplexer includes low-impedance voltage switches, at least one of which includes a well-voltage select circuit. The well-voltage select circuit adjusts the well bias on a power-switching transistor, and consequently protects the power-switching transistor from damage caused by gate breakdown and forwarding biasing of the well.

Power multiplexer and switch with adjustable well bias for gate breakdown and well protection

A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

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Castro Valley, CA, United States of America

Henry A Om'mani