International Business Machines Corporation

Henry A Bonges, Iii

Terence B Hook

David L Harmon

Wing L Lai

Dureseti Chidambarrao

Jason D Hibbeler

Stephen Edward Greco

Erik L Hedberg

Michael S Gray

Kevin W McCullen

Douglas Wayne Kemerer

Robert F Walker

Jeffrey Scott Zimmerman

Tina Jane Wagner

James W Dawson

Robert Dean Adams

Roy Childs Flaker

David C Reynolds

William F Pokorny

James E Sundquist

Albrik Avanessian

Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.

System and method to improve chip yield, reliability and performance

A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an 'intersect area,' of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

Intersect area based ground rule for semiconductor design

A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

Determining allowance antenna area as function of total gate insulator area for SOI technology

A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number of neighboring cells which must be explored. In every fourth iteration of the expansion process, corner cells may not be expanded. Reachable areas outside of conductors can also be explored.

Method of performing latch up check on an integrated circuit design

Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage

A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

Cloned and original circuit shape merging

A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.

Module level electronic redundancy

A BiCMOS output driver in which a bipolar device is driven by a control signal that biases the collector of an NFET. The control signal enables the bipolar to pull an output node to full potential (ground) quickly. The signal then falls within one nanosecond after the output reaches ground, pulling the bipolar out of saturation. A separate feedback device coupled between the base of the bipolar and ground can be added to pull the bipolar out of saturation before the control signal falls.

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Milton, VT, United States of America

Henry A Bonges, Iii