Broadcom Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Henrik Tholstrup Jensen

Brima Babatunde Ibrahim

Hea Joung Kim

Hooman Darabi

Alireza Zolfaghari

Hong Shi

Stephen Wu

Siukai Mak

Paul Anthony Lettieri

Georgios Sfikas

Emmanouil Frantzeskakis

Ahmadreza Rofougaran

Seema Butala Anand

Radha Srinivasan

Aminghasem Safarian

Jianhua Gan

Louie Serrano

Ioannis Loukas Syllaios

Hyungpyo Lee

Prasanna Desai

Shahla Khorram

Robert Hulvey

Michael Kappes

Angel Arturo Polo

Thomas Francis Baker

Guoxin Xie

Jared Welz

Behnam Mohammadi

Yushi Tian

Ming Yu Lin

Amir Ibrahim

Tom Baker

Philippe Riondet

Jianfeng Shi

Manolis Frantzeskakis

Eric Raith

Farooq Muhammad Hameed

Georgios Srikas

Padmanava Sen

The present disclosure describes various chassis based antennas for a communication device. These various chassis based antennas can be integrated within a mechanical chassis of the communication device. The mechanical chassis is at least partially constructed of one or more conductive materials, such as copper or aluminum to provide some examples, or combinations of conductive materials, to provide one or more conductive paths for the communication device. The communication device can use these one or more conductive paths as one or more chassis based antennas for communication.

Chassis based antenna for a near field communication (NFC) enabled device

A communication device used for near filed communications (NFC). The device includes circuitry that generates a differential signal for communication with an analog front end of the device. The analog front end includes an impedance matching network and an antenna. The antenna is disposed at a predetermined distance away from the boundary of a battery compartment. The antenna forms a single loop around the battery compartment and is coupled to the matching network either in a differential manner or a single ended manner. The communication device includes a protective back casing that is either metallic or plastic in nature. With the single loop antenna configuration, both types of back covers enable efficient NFC.

Chassis NFC antenna booster

A method of communicating data in a Bluetooth&#x2122; low energy (BLE) module is provided. The method includes modulating an outbound communication signal into a modulated signal with a particular modulation scheme based on a modulation type, and transmitting the modulated signal to a remote device via a wireless communication connection associated with the modulation type. The method also includes receiving an inbound radio frequency (RF) signal, determining if the inbound RF signal is associated with a modulation type, and demodulating the inbound RF signal with a particular modulation scheme based on the modulation type if the inbound RF signal is determined to be associated with a modulation type. In some aspects, the inbound RF signal and outbound modulated signal have symbol rates of 2 Megasymbols per second. In some implementations, the method includes switching between a legacy BLE system and an enhanced rate BLE system.

Enhanced rate physical layer for Bluetooth&#x2122; low energy

Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (&#x394;&#x3a3;) phase/frequency detector (&#x394;&#x3a3; PFD). A hybrid 2nd-order &#x394;&#x3a3; PFD may be implemented based on a continuous-time 1st-order &#x394;&#x3a3; analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the &#x394;&#x3a3; PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced &#x394;&#x3a3; quantization noise. The implementation of low complexity &#x394;&#x3a3; PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

Digital PLL with hybrid phase/frequency detector and digital noise cancellation

Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency hands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Multi-mode analog-to-digital converter

A method and system for packet synchronization may comprise receiving a plurality of bits from an incoming sample of data. The received plurality of bits may be sliced at a first sampling rate. A logic level of at least one of the received plurality of bits may be determined based on the slicing of the received plurality of bits. The received plurality of bits may be synchronized with a channel access code based on determining the logic level of at least one of the received plurality of bits. The channel access code may be sampled at a higher frequency, to increase the probability of detecting whether the incoming bit is LOGIC 1 or LOGIC 0.

Method and system for packet synchronization

Techniques and devices are disclosed to provide multi-stage gain control in circuits or devices having two or more stages of signal amplification. A circuit with multi-stage gain control can include amplification stages coupled to receive an input signal and to produce an amplified output signal. Each amplification stage includes an amplifier that is adjustable in gain and a signal detector that is coupled to measure an output signal of the amplifier and to produce a detector signal indicative of a signal strength of the output signal of the amplifier. A gain control circuit is coupled to receive detector signals from the signal detectors in the amplification stages, respectively, and to control gains of the amplifiers of the amplification stages based on respective received detector signals, respectively.

Multi-stage gain control in receivers and other circuits

Various embodiments are disclosed relating to power control techniques for wireless transmitters. In an example embodiment, an apparatus is provided that may include a digital-to-analog converter (DAC) adapted to convert a digital amplitude signal to an analog amplitude signal during a first transmission mode and adapted to convert a digital power level signal to an analog power level signal during a second transmission mode.

Power control techniques for wireless transmitters

The present disclosure is directed to a method and apparatus for providing an output oscillating signal at a desired frequency. In at least one example, the apparatus includes a weak inversion structure configured to set a small reference current. A current mirror configured to provide a replica current based on the small reference current and a tuning word. A ring oscillator is configured to be powered by a supply at a voltage determined based on the replica current. The tuning word is adjustable to change the voltage such that the ring oscillator provides the output oscillating signal at the desired frequency.

Frequency synthesis using a ring oscillator

Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Digital phase locked loop with feedback loops

The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.

Digital phase-locked loop with wide capture range, low phase noise, and reduced spurs

A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Digital delta Sigma modulator and applications thereof

Digital phase locked loop circuits

Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency bands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Digital phase locked loop circuits with multiple digital feedback loops

Growing community of inventors

Long Beach, CA, United States of America

Henrik Tholstrup Jensen