Telefonaktiebolaget Lm Ericsson (publ)

St-ericsson Sa

Henrik Sjöland

Stefan Mikael Andersson

Tony Påhlsson

Johan Wernehag

Imad Ud Din

Leif Wilhelmsson

Staffan Ek

Mohammed Abdulaziz

Lars Sundström

Tobias Tired

Christian Elgaard

Henrik Fredriksson

Daniel Eckerbert

Miguel Lopez

Fredrik Tillman

Martin Anderson

Gang Zou

Carl Bryant

Waqas Ahmad

Andres Reial

Anders Wallén

Magnus Åström

Sven Erik Mattisson

Magnus Norberg Olsson

Sina Maleki

Fenghao Mu

Magnus Sandgren

Torbjörn Sandström

Jonas Lindstrand

Thomas Rimhagen

Jim Svensson

Piergiuseppe Di Marco

Pramod Jacob Mathecken

Mattias Palm

Fredrik Dahlgren

Andreas Axholt

Ashkan Kalantari

Bengt Edholm

Mohammed Zourob

Florent Torres

Reda Kasri

Razvan-Cristian Marin

Torbjorn Sandstrom

Kittichai Phansathitwong

Stefan Andersson

Johan Wernerhag

A quadrature oscillator according to the embodiments herein comprising two pairs of main transistors, two pairs of resonators and two pairs of injection transistors. The quadrature oscillator is split into two halves, which are separated in the chip layout. That is the two pairs of resonators are separated from each other, and the two pairs of the main transistors are separated from the resonator they coupled to such that the quadrature oscillator is separated into two spaced apart oscillator halves connected by transmission lines.

Quadrature oscillator

A method is disclosed—for a wireless communication device served by a network access node—of keeping a time reference at the wireless communication device. The wireless communication device is configured for operation according to at least first and second operational modes, the second operational mode having lower power consumption than the first operational mode. The method comprises (during operation according to the first operational mode) determining (for the second operational mode) desired timings of timing signals to be transmitted from the network access node, and transmitting a request signal to the network access node, wherein the request signal carries information of the desired timings of timing signals to be transmitted from the network access node. In some embodiments, the method further comprises receiving a response signal from the network access node, wherein the response signal carries information of actual timings of timing signals to be transmitted from the network access node. Corresponding method for a network access node, apparatuses, wireless communication device, network access node and computer program product are also disclosed.

Keeping a time reference

An integrated, distributed, multiple Phase Locked Loop (multi-PLL) system locks the frequency and phase of multiple secondary PLLs to that of a primary PLL. The VCOs in all PLLs receive both first and second control signals. The primary PLL's primary VCO control signal is generated conventionally. using a reference periodic signal input, and is output to all secondary PLLs: hence the secondary PLLs operate at the primary PLL frequency. The primary PLL also outputs its divided periodic signal. Each secondary PLL compares its local divided periodic signal to the one received from the primary PLL (rather than to a reference signal input) in its phase locking loop. generating a secondary VCO input that locks the secondary PLL circuit phase to that of the primary PLL circuit. Selected secondary PLLs can be set to a phase offset from the primary PLL, such as by controlled DC current injected into the charge pump output. Phase noise generated by the primary PLL VCO is detected and corrected by one or more secondary PLLs in a second charge pump circuit that outputs a correction current having an inverse polarity. The correction currents are summed, and a correction loop filter generates a third VCO control signal which is provided to the second primary VCO input to correct the phase noise. Either the charge pumps scale output current (1/N) or the correction loop filter scales impedance (1/N) to account for the number (N) of secondary PLLs generating correction currents. A common mode voltage circuit may monitor selected VCO control signals of all PLLs. and maintains the common mode input level within a predetermined voltage range.

Multiple PLL system with phase locking and phase noise cancellation

The present invention relates inter alia to a transmitter arrangement (), in particular for radio communication, comprising at least two antenna elements (), spaced apart by a defined distance and a differential output amplifier () with a first output () coupled to a first () of the at least two antenna elements () and with a second inverted output () coupled to a second () of the at least two antenna elements (). A first transmission line element () is arranged between at least one of the first and second outputs () and the respective one of the at least two antenna elements () and is configured such that signals applied to respective input taps () of the at least two antenna elements () are substantially in-phase with each other.

Transmitter arrangement, transceiver, radio communication system and method

A method for a wake-up transmitter comprises generating a wakeup signal (WUS) from a digital WUS sequence having an information symbol rate and a corresponding information symbol bandwidth, and transmitting the WUS over a frequency range having a signal bandwidth, wherein the signal bandwidth is larger than twice the information symbol rate, and wherein any frequency interval comprised in the frequency range conveys the digital WUS sequence when a width of the frequency interval is at least the information symbol bandwidth. A corresponding method for a wake-up receiver comprises receiving the WUS over the frequency range, and filtering the received WUS through a filter having a filter bandwidth for passing the information symbol bandwidth of the received WUS. Corresponding apparatuses, wake-up transmitter, wake-up receiver, communication device and computer program product are also disclosed.

Wake-up signal, and corresponding transmitter and receiver

A wireless communication node () and method therein for generating and transmitting a modulated radio frequency (RF) signal by means of backscattering are disclosed. The wireless communication node () comprises an antenna () configured to receive a illuminating RF signal, a switch () that has M states, a set of impedances () comprising Mimpedances (Z1, Z2 . . . ZM). The antenna () is coupled to the set of impedances () by the switch (). The wireless communication node () further comprises a modulating value generator () configured to generate modulating values based on data to be transmitted and a frequency offset and a switch controller () configured to switch the state of the switch () based on the generated modulating values such that the antenna () is connected to a selected impedance among the M impedances. The received illuminating RF signal at the antenna () is modulated by the generated modulating values and reflected by the antenna () to generate and transmit the modulated RF signal. The switching rate is an integer multiple of the data rate, the integer is greater than 1 and the center frequency of the modulated RF signal has the frequency offset with respect to the center frequency of the received illuminating RF signal.

Communication node and method for generating modulated signals by backscattering

A method performed in a base station for frequency calibration of a receiver is disclosed. The base station generates a first signal with periodic ASK modulation and transmits the first signal as a preamble or frequency marker signal to facilitate frequency calibration of the receiver. The receiver sweeps its oscillator frequency to detect if there is a preamble or frequency marker signal present. When it is determined that there is a signal present, the oscillator frequency of the receiver is calibrated to the transmitting frequency of the base station. The base station then transmits a second signal as a wakeup signal to the receiver.

Preamble signal for wakeup communication in a wireless communication system

A method of signal block reception with automatic gain control (AGC) for a receiver is disclosed. The receiver is configured for at least a sleep mode and an active mode. The signal blocks are non-adjacent in time, and each signal block is configured to be received in entirety using a valid AGC setting determined based on a previous signal block. The method comprises, when switching from the sleep mode to the active mode for continuous reception of a signal block, receiving a first set of samples of the signal block, determining an applicable AGC setting based on the first set of samples of the signal block, and receiving a second set of samples of the signal block using the applicable AGC setting determined based on the first set of samples. Corresponding apparatus, receiver, wireless communication device and computer program product are also disclosed.

Signal block reception with automatic gain control adjustment

A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and third transistors are biased by a first voltage.

Bias circuit and power amplifier circuit

An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals and to provide first and second outputs based on the first and second input signals. A difference in pulse length between signals provided at the first and second outputs is indicative of the phase difference between the first and second input signals. The apparatus also comprises first and second time-to-digital converters (TDCs) each configured to receive one of the signals provided by the PFD and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC, wherein pulse length modification may comprise pulse length shrinking or pulse length extension. The apparatus also comprises a comparator configured to provide the indication of the phase difference based on the digital pulse length representations provided by the first and second TDCs. Corresponding digital phase-locked loop (DPLL) and communication device are also disclosed.

Apparatus for digital representation of angular difference

A wireless communication device () comprises a first transceiver () comprising a first frequency synthesizer () which comprises a first digitally controlled oscillator (DCO) and a crystal oscillator (XO). The wireless communication device () further comprises a second transceiver () comprising a wakeup receiver (Rx), a second transmitter (Tx) and a second digitally controlled oscillator (DCO) connected to the wakeup receiver (Rx) and second transmitter (Tx). The wireless communication device () further comprises a control unit () configured to control operation of the wireless communication device. The second transmitter (Tx) is configured to transmit periodically a signal to a base station. The signal is modulated by a code identifying the wireless communication device () and transmitted at a frequency set by the second digitally controlled oscillator (DCO).

Wakeup communication in a wireless communication system

An analog PLL employs digital circuitry for calibration and characterization, precisely setting and maintaining the bandwidth of the PLL. A digital calibration circuit calibrates the value of a resistor or capacitor in the loop filter to yield a desired RC product. A digital control circuit reads time-to-digital converters (TDC) digitizing the length of the CU and CD pulses from the phase-frequency detector (PFD) to the charge pump (CP) during a frequency change. These pulse lengths are summed to yield a measured integral CP current. The control circuit determines an integral CP current that yields a desired bandwidth, regardless of the VCO tuning sensitivity, based on the calibrated RC product. The CP current is then adjusted by the ratio of determined integral CP current to the measured integral CP current. The digital circuits do not increase power consumption or adversely affect system operation.

Digitally augmented analog phase locked loop with accurate bandwidth

A method of establishing connection between a first node in a wireless network and a second node in said wireless network, wherein each of said first and second nodes comprise a primary radio receiver and a wake up receiver, each of said nodes comprising a Radio Frequency, RF, switch, arranged to connect one of said primary or secondary radios to a radio antenna, said method comprising the steps of transmitting, by said first node, to a wake-up receiver of a second radio node, a wake-up signal that indicates a frequency channel on which the second radio node is to transmit a response, receiving, by said first node, in response to transmitting said wake-up signal, response from said second radio node on the frequency channel indicated, and establishing, by said first node, a connection between said first and second nodes in order to transfer data between said first and second nodes. The present disclosure also relates to corresponding mesh nodes and a computer program product.

Use of wake-up receiver with Bluetooth low energy

A beamforming apparatus () performs beamforming via a plurality of antenna elements () by using per-branch sign reversal circuits () that approximate the per-branch phase values associated with a particular beam direction or shape by selectively reversing or not reversing the polarities of the individual branch signals (). Eliminating continuous-valued or high-resolution phasing control from the branch circuits () that are fed into or from the respective antenna elements () simplifies the branch circuitry, thereby reducing the physical space needed for the branch circuits () and reducing loss and noise within the branch circuits (). Further, operating the plurality of antenna elements () as two or more groups () and controlling the differential phase between the groups () advantageously reduces the errors arising from the approximation of the per-branch phase values.

Beamforming method and apparatus

A transmitter circuit has a signal input for receiving an analog input signal and a local oscillator (LO) input for receiving an LO signal. A mixer circuit has a first input, a second input, and an output. The second input of the mixer circuit is connected to a signal input of the transmitter circuit. A PA circuit has an input connected to the output of the mixer circuit, and an output. A control circuit generates a phase-control signal and a gain-control signal in response to an envelope of the analog input signal. A phase-control circuit generates a phase-adjusted LO signal in response to the LO signal and the phase-control signal and supplies the phase-adjusted LO signal to the first input of the mixer circuit. A gain-control circuit controls a gain of the transmitter circuit in response to the gain-control signal.

Transmitter circuit

Growing community of inventors

Lund, Sweden

Henrik Sjöland