Infineon Technologies Ag

Ericsson Gmbh

Henrik Hoyer

Larry C Leighton

Thomas W Moller

Donald Fowlkes

Bengt Ahl

Jochen Dangelmaier

Volker Guengerich

Tom Moller

Jeff Hume

Sam-Hyo Hong

Bradley Griswold

Jeffrey Hume

An RF power amplifier including a single piece heat sink and an RF power transistor die mounted directly onto the heat sink.

Power amplifier

A semiconductor device () has gold coatings (to) which are applied to metallic or ceramic components () of the semiconductor device (). The gold coatings (to) have a multifunctional multilayer metal coating () with a minimal gold layer (). The gold layer has a thickness dwhere d&#x2266;0.5 &#x3bc;m. Moreover, at least one metallic interlayer () is arranged between the gold layer () and the metallic or ceramic components ().

Semiconductor device with gold coatings, and process for producing it

In a circuit, an integrated circuit package and methods for attaching integrated circuit dies or discrete power components to flanges of integrated circuit packages, each of the integrated circuit dies is sawed from a wafer. The thickness of the wafer is reduced by mechanical grinding, applying an isotropic wet chemical etching to the wafer to eliminate crystal defects, evaporating adhesion and diffusion barrier metals on the backside of the wafer, evaporating Au and Sn on the backside of the wafer, wherein the weight proportion of Au is equal to or larger than 85%, sawing the wafer into the circuit dies, and soldering each of the circuit dies to a respective flange of an integrated circuit package.

Highly reliable, cost effective and thermally enhanced AuSn die-attach technology

A laterally diffused metal oxide semiconductor (LDMOS) power package includes a conductive mounting flange mounted on a heat sink and electrically connected to a dielectric substrate of a printed circuit board. A plurality of transistors are mounted on the top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths are provided to electrically couple the top surface of the mounting flange to the dielectric substrate, thereby reducing resistance and inductance in the ground signal path and increasing the efficiency of the power package.

Multiple ground signal path LDMOS power package

An LDMOS power package includes a mounting substrate having a surface with one or more alignment pedestals extending therefrom. Each alignment pedestal has a mounting surface facing away from the substrate surface to provide for uniform positioning of various semiconductor elements, e.g., a transistor die or impedance matching capacitors, relative to the substrate surface. The respective pedestal mounting surfaces are preferably conductive, and are electrically coupled to the flange surface, so as to electrically couple the respective capacitor and electrode ground terminals to the flange.

Alignment pedestals in an LDMOS power package

A packaged integrated circuit device includes a substrate including a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component. The second circuit component may comprises an impedance matching circuit. The circuit device may also include fastening means for securing the lid to the substrate. The fastening means may comprise an adhesive, solder, or a spring biased member.

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Los Gatos, CA, United States of America

Henrik Hoyer