Telefonaktiebolaget Lm Ericsson (Publ)

Henrik Fredriksson

Henrik Sjöland

Martin Anderson

Lars Sundström

Fredrik Tillman

A method of weight calibration in a DAC () is disclosed. The DAC () comprises an input port () for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit () configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Z) in the control word (z[n]) has a corresponding bit weight (w) and is in the following considered to adopt values in {−1, 1}. Furthermore, the DAC () comprises a set () of analog weights, each associated with a unique one of the bits (Z) in the control word (z[n]), and summation circuitry () configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Z) weighted by the respective associated analog weights. The DAC () also has an output () for outputting the analog sample. The method comprises, during a measurement procedure, for a first set of at least one bit of the control word (z[n]), generating () the bits of the first set, such that a first sum of the bits in the first set weighted by their respective bit weights is, on average, above zero. Furthermore, the method comprises, during the measurement procedure, for a second set of at least one bit of the control word (z[n]), generating () the bits of the second set, such that a second sum of the bits in the second set weighted by their respective bit weights is, on average, below zero and such that the sum of the first sum and the second sum is, on average, equal to zero. The method also comprises detecting () a DC level at the output of the DAC during the measurement procedure. The method further comprises adjusting () at least one analog weight in response to the detected DC level. A corresponding DAC, a corresponding electronic apparatus, and a corresponding integrated circuit are also disclosed.

DAC weight calibration

An ADC circuit () is disclosed. It comprises a global input configured to receive an input voltage (V) and a plurality of converter circuits (-). Each converter circuit () comprises a comparator circuit () having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (). Furthermore, each converter circuit () comprises a one-bit current-output DAC () having an input directly controlled from the output of the comparator circuit () and an output connected to the second input of the comparator circuit (). The second inputs of all comparator circuits are interconnected. The ADC circuit () further comprises a digital output circuit () configured to generate an output signal z[n] of the ADC circuit () in response to the one-bit output signals of the comparator circuits ().

Analog-to-digital converter circuit

A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.

Signal generator with direct digital synthesis and tracking filter

A digital-to-analog conversion circuit () for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, () wherein the first DAC () is of a capacitive voltage division type having a capacitive load (). Furthermore, it comprises a second DAC () having a resistive load (). An output () of the first DAC () and an output () of the second DAC () are connected, such that said capacitive load () and said resistive load () are connected in parallel.

Digital-to-analog conversion circuit

The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample. Corresponding TI-ADC, wireless communication receiver, wireless communication node, method and computer program product are also disclosed.

Control of a time-interleaved analog-to-digital converter

A DAC () is disclosed. It comprises an input port comprising N input terminals p, p, . . . , pconfigured to receive voltages representing N input bits b, b, . . . , b, respectively, wherein the significance of bis higher than for bfor j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit () comprising N capacitors C, C, . . . , Cwith capacitance C, each having a first terminal and a second terminal. Capacitor Cis connected with its first terminal to the terminal pof the input port. For each j=1, 2, . . . , N&#x2212;1, the capacitor ladder circuit () comprises a capacitor () with capacitance xC connected between the second terminal of capacitor Cand the second terminal of capacitor C. The DAC () also comprises an input circuit () connected to the input port comprising at least one capacitor (-), each connected between a unique one of the input terminals p, p, . . . , pof the input port and signal ground.

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Lund, Sweden

Henrik Fredriksson