Intel Corporation

Henrietta Bezbroz

Alexander Gendler

Ohad Falik

Michael Behar

Israel Diamand

Roni Rosner

Zigi Walter

Oz Shitrit

Shlomi Alkalay

Ravi Venkatesan

Shlomi Shua

Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.

Methods and apparatus to implement multiple inference compute engines

In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.

Processor having concurrent core and fabric exit from a low power state

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Or-Aqiva, Israel

Henrietta Bezbroz