Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Leland Stanford Junior University

Henri-Pierre Charles

Jean-Philippe Noel

Maha Kooli

Suzanne Lesecq

Pascal Vivet

Subhasish Mitra

Lionel Vincent

Roman Gauchi

Kevin Mambu

Stephane Mancini

The present description concerns a system comprising at least one first and one second memory circuits; and a direct data transfer circuit which is adapted to receiving specific instructions originating from an external processor, and to decoding specific instructions comprising: a specific instruction SET_REGION of definition of a sub-region in the first memory circuit towards and from which the data will be transferred; and a specific instruction of transfer between said sub-region and the second memory circuit, the specific transfer instruction comprising a first address field containing the relative coordinates, in said sub-region, of a first reference cell.

Direct data transfer system

The present description concerns a memory module () adapted to implementing computing operations, the module comprising a plurality of elementary blocks () arranged in an array according to rows and columns, wherein: each elementary block () comprises a memory circuit () adapted to implementing computing operations, and a configurable transfer circuit (); each configurable transfer circuit () is parameterizable to transmit data originating from a first transmit elementary block to a receive elementary block of a same column of elementary blocks via at least one link bus; an internal control circuit () is connected to an input-output port () of the module; and the internal control circuit () is configured to read at least one instruction signal from the input-output port () of the module and accordingly parameterize the configuration of the configurable transfer circuits (), and define the size of the operand vectors of the computing operations.

Reconfigurable memory module designed to implement computing operations

A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.

Memory circuit capable of implementing calculation operations

A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

System comprising a memory capable of implementing calculation operations

A datum to be preloaded includes the acquisition of a, so-called 'model', statistical distribution of the deltas of a model access sequence, the construction of a, so-called 'observed', statistical distribution of the deltas of an observed access sequence, the identification in the observed statistical distribution, by comparing it with the model statistical distribution, of the most deficient class, that is to say of the class for which the difference NoDSM&#x2212;NoDSO is maximal, where NoDSM and NoDSO are the numbers of occurrences of this class that are deduced, respectively, from the model statistical distribution and from the observed statistical distribution, the provision as prediction of the datum to be preloaded into the cache memory, of at least one predicted address where the datum to be preloaded is contained, this predicted address being constructed on the basis of the most deficient class identified.

Growing community of inventors

Grenoble, France

Henri-Pierre Charles