International Business Machines Corporation

Henri Giuliano

Jean-Francois Le Pennec

Patrick Michel

Alain Benayoun

Patrick Sicsic

Jean-marc Cazaentre

Alain Brun

The invention provides an impedance adapter that automaticaly switches to impedances that match network transmit/receive lines impedances (105,106) by a controlled switching of various impedances mounted serially/parallely with connected transmitter/receiver (100,101). For a high speed adapter, a balanced transmitter/receiver is required for limiting crosstalk effect due to the high transmission rate. Transmit/Receive impedance adaptation networks (102-103) are composed of serial/parallel networks of resistors and relay contacts that are switched independently by magnetic coils of an impedance switching circuit (110) and having values conformable to the various network impedances imposed by different national regulations. By using the principle of double deviation voltage technique, a measuring circuit (108) detects upward and downward voltages (VA,VB), VB amplified by 2 to generate an analog signal VS (VS=VA-2VB) to a control logic circuit (109). This circuit (109) determines if the resistors value selected by the magnetic coils of said impedance switching circuit (110) is equal or not equal to the impedance of the network lines (106,105). Thus, it compares VS to a voltage Vref (25) to generate an output which selects and activates the correct magnetic coil for changing or keeping equal the resistors of the receive/transmit impedance network (102,103) currently connected to the network lines (105,106).

Impedance adapter for network coupler cable

An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time. The adapter further includes means for resetting the line interface circuits and the DPLL at the power-on of the adapter, such that the frequency correction apparatus of the adapter causes two adapters attached at separate ends of a transmission medium to evolve toward stable timing states with respect to each other.

Adapter for the connection to a clear-channel telecommunication network

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Vence, France

Henri Giuliano