Infineon Technologies Ag

International Business Machines Corporation

Infineon Technologies North America Corp.

Other

Advanced Mask Technology Center Gmbh + Co. Kg

Henning Haffner

Richard Lindsay

Manfred Eller

Scott Marshall Mansfield

Alois Gutmann

Chandrasekhar Sarma

Sajan Marokkey

Shahid Ahmad Butt

Zachary Baum

Louis L Hsu

Jiang Yan

Scott David Halle

Haoren Zhuang

Gunther Lehmann

Michael E Scaman

Klaus Schruefer

Frank Huebinger

Josef Maynollo

Jason E Meiring

Armin Semmler

Armin M Reith

Lars W Liebmann

Matthew Earl Colburn

Chandrasekhar Narayan

Dominique Savignac

Heinz Hoenigschmid

Allen H Gabor

Hans-Peter Moll

Martin Ostermayr

Derren Neylon Dunn

Sun-Oo Kim

Axel Christoph Brintzinger

Donald J Samuels

Matthias Lipinski

Alan C Thomas

Torsten Franke

Werner Graf

Helen Wang

Klaus Herold

Lars Heineck

Ramya Viswanathan

Steffen Schulze

Amr Y Abdo

Sabine Kling

Roderick Koehle

Michael M Crouse

Christian Rotsch

Christoph Friedrich

Uwe Dersch

Martin Verbeek

Sunoo Kim

Norbert Haase

Beate Frankowsky

Johannes Kowalewski

Elke Hietschold

Oseo Park

Karin Eggers

Andreas Frangen

Carmen Jaehnert

Bettine Buechner

Ines Anke

Fred L Einspruch

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Integrated circuits and methods of design and manufacture thereof

A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Silicided semiconductor structure and method of forming the same

A method includes depositing a material layer over a semiconductor substrate and using a first mask in a first exposure/patterning process to pattern the material layer thereby forming a plurality of first and second features. The first features include patterns for the semiconductor device and the second features include printing assist features. The method includes using a second mask in a second exposure/patterning process to effectively remove the second features from the material layer and to define at least one separating structure between two first features.

Method for defining a separating structure within a semiconductor device

A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.

Mask layout formation

Multi-beam lithography systems and methods of manufacturing semiconductor devices using the same are disclosed. For example, the method utilizes non-coincidence of boundaries of electrical fields emanating from chrome on glass or phase shifted mask features distributed over two masks for the optimization of lithographic process windows, side lobe suppression, or pattern orientation dependent process window optimization employing one mask with polarization rotating film on the backside.

Lithography systems and methods of manufacturing using thereof

In accordance with an embodiment of the present invention, a method for making a semiconductor device comprises forming a photo sensitive layer on a semiconductive substrate, and forming an L-shaped structure in the photo sensitive layer by exposing the photo sensitive layer to light via a reticle, wherein the reticle comprises an L-shapes feature having a first non-orthogonal edge at an intersection of two legs of the L-shaped feature.

L-shaped feature, method of making an L-shaped feature and method of making an L-shaped structure

Aspects of the invention include a computer-implemented method of designing a photomask. In one embodiment, the method comprises: simulating a first photomask patterning process using a first photomask design to create simulated contours; comparing the simulated contours to a desired design; identifying regions not common to the simulated contours and the desired design; creating desired target shapes for a second photomask patterning process subsequent to the first photomask patterning process based upon the identified regions; and providing the desired target shapes for forming of a second photomask design based upon the desired target shapes.

Generating cut mask for double-patterning process

A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.

Calibration and verification structures for use in optical proximity correction

Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated with one or more printing assist features (PrAFs); adding the one or more PrAFs of the set of parameters to the design layout to produce a modified design layout; performing simulation of the one or more PrAFs and the one or more designed features on the modified design layout; verifying whether the one or more PrAFs are removable based on results of the simulation; and creating a set of PrAF placement rules based on the set of parameters, if the one or more PrAFs are verified as removable. The set of PrAF placement rules may be used in creating a final set of PrAF features to be used for creating the mask layout.

Methodology of placing printing assist feature for random mask layout

A mask and method for patterning a semiconductor wafer is disclosed. A mask set is fabricated on a transparent substrate. A mask layer comprising mask region elements that transmit light is disposed on the substrate, wherein each mask element is segmented into a plurality of segments.

Mask and method for patterning a semiconductor wafer

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Pawling, NY, United States of America

Henning Haffner