Intel Corporation

Tahoe Research, Ltd.

Henning Braunisch

Johanna M Swan

Aleksandar Aleksov

Adel A Elsherbini

Georgios C Dogiamis

Shawna M Liff

Telesphor Kamgaing

Feras Eid

Daoqiang Lu

Sujit Sharan

Kemal Aygun

Krishna Bharath

Brandon M Rawlings

Neelam Prabhu Gaunkar

Gilroy J Vandentop

Diego Correas-Serrano

Chia-Pin Chiu

Stefanie M Lotz

Hinmeng Au

Veronica Aleman Strong

Richard J Dischler

Yidnekachew S Mekonnen

Zhiguo Qian

Mathew J Manusharow

Anna M George, Legal Representative

Javier Soto

Patrick R Morrow

Paul B Fischer

Kristof Darmawikarta

Kimin Jun

Zhichao Zhang

Peter Chang

Javier Soto Gonzalez

Thomas L Sounart

Brennen Karl Mueller

Hyung-Jin Lee

Sasha N Oster

William J Lambert

Prithwish Chatterjee

Beomseok Choi

Ajay Jain

Stephen L Morein

Mauro J Kobrinsky

Sanka Ganesan

Stefano Pellerano

Bruce A Block

Fay Hua

Kenneth Edward Salsman

Andrew James Brown

Cynthia S Bell

Steven N Towle

Javier A Falcon

Raj Nair

Edris M Mohammed

Eric C Palmer

Chandrashekhar Ramaswamy

Don W Nelson

Gilbert W Dewey

Ian A Young

Kaan Oguz

Kevin O'Brien

Ravindranath Vithal Mahajan

Chuan Hu

Kaladhar Radhakrishnan

Peter L D Chang

Hengju Cheng

Thomas Dory

Rajashree Raji Baskaran

Yikang Deng

Shan X Wang

Rajendran Nair

Andrew Paul Collins

Jianyong Xie

Jeff C Morriss

Mark B Trobough

Andrew Alduino

Kevin P O'brien

I-Cheng Tung

Chintan S Thakkar

Cho-Ying Lu

Arnab Sarkar

Anna M George

Ajay Balankutty

John Tang

Timothy A Gosselin

Prasanna Raghavan

Bram Leader

Arghya Sain

Ahmed Abou-Alfotouh

Said Rami

Ankur Mohan Crawford

Thomas W Brown

Cooper S Levy

Gloria Alejandra Camacho Bragado

Prashant D Parmar

John S Cuendet

Nathan Fritz

Victor J Prokoff

Nathaniel Arbizu

Victor Prokoflev

Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Substrate integrated thin film capacitors using amorphous high-k dielectrics

Apparatus and methods of manufacture are disclosed. In one example the apparatus includes a first substrate that has a first surface, a first optical waveguide that is at or near the first surface of the first substrate, a second substrate that has a second surface. The second substrate is coupled to the first substrate at an interface. The apparatus also has a photonic integrated circuit (PIC) with a portion at or near the second surface. The PIC is in alignment with and optically coupled to the first optical waveguide across the interface.

Apparatus and method of manufacturing a vertically disaggregated photonic device

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

Cooling of conformal power delivery structures

Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

Components for millimeter-wave communication

Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.

Low leakage thin film capacitors using titanium oxide dielectric with conducting noble metal oxide electrodes

In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

High-density interconnects for integrated circuit packages

An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

Microelectronic assemblies

An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

High-throughput additively manufactured power delivery vias and traces

Embodiments may relate an electronic device that includes a first server blade and a second server blade coupled with a chassis. The first and second server blades may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first and second server blades such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

Platforms including microelectronic packages therein coupled to a chassis, where waveguides couple the microelectronic packages to each other and usable in a computing device

Millimeter-wave dielectric waveguide bundle including first and second adjacent dielectric waveguides having different core and/or cladding materials

Millimeter-wave dielectric waveguide including an opening of varying cross-section enclosed within a first material and the first material surrounded by a second material

A multi-chip package includes a substrate () having a first side (), an opposing second side (), and a third side () that extends from the first side to the second side, a first die () attached to the first side of the substrate and a second die () attached to the first side of the substrate, and a bridge () adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity () in the substrate or between the substrate and a die layer (). The bridge may constitute an active die and may be attached to the substrate using wirebonds ().

Multi-chip package and method of providing die-to-die interconnects in same

Growing community of inventors

Phoenix, AZ, United States of America

Henning Braunisch