U.S. Philips Corporation

Henk W Begas

Jan Van Der Meer

Franciscus W Vreeswijk

Timothy I Trew

A transmitting section of the system according to the invention has transmitting section signal paths for at least three classes of motion, each with a preprocessing circuit (143, 145 and 147) which are provided with means for individually sampling. These sampling means sample in accordance with separate sampling patterns so that each preprocessing circuit (143, 145 or 147) supplies a video signal which is suitable for a display with an optimum distribution of temporal and/or spatial resolution for the associated class of motion. Dependent on the class of motion determined, one of the preprocessing circuits (143, 145 or 147) is coupled to a channel (170). The video signal to be supplied to the channel (170) is therefore a video signal suitable for a display with an optimum distribution of temporal and/or spatial resolution for the given class of motion (FIG. 1A). A high-definition receiving section of the system according to the invention also has at least three receiving section signal paths comprising a postprocessing circuit (43, 45 and 47) which decodes a received video signl in accordance with a method associated with the relevant postprocessing circuit (43, 45 or 47). The correct postprocessing circuit (43, 45 or 47) is selected in accordance with the class of motion, so that in the receiving section of the system according to the invention a display with an increasing spatial resolution can be achieved in the case of a decreasing motion (FIG. 1B).

Method and apparatus for temporally and spatially processing a video

A level indicator for displaying the decibel values of digital samples of an analog signal with respect to a reference value, each sample having a predetermined number of bits. The indicator comprises a shift register having a smaller bit capacity than the number of bits in the digital signals and for which, a resolution of 2dB, comprises three series-connected flip-flops. The digital signals are applied to the input of the first flip-flop and, together with the outputs of all the flip-flops, to a combinational logic circuit. The output of the last flip-flop is connected to a read-enable circuit. As each bit of a digital signal is shifted into the shift register, the logic circuit generates a logic signal from combination of the output signals of the flip-flops and such digital signal bit, the value of such logic signal indicating how many times a predetermined decibel amount should be applied to the value stored in the shift register in order to attenuate it to the reference value. An adder adds the value of such logic signal to the value of the logic signal previously produced by the logic circuit in response to the preceding bit of the digital signal, and the resulting sum is stored in a memory. When the number of digital signal bits in the shift register reaches the capacity of the shift register, the sum then in the memory is transferred to a read-out device by the read-enable circuit.

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Eindhoven, Netherlands

Henk W Begas