Intel Corporation

Henk G Neefs

Sailesh Kottapalli

Rahul Pal

Manoj K Arora

Vedaraman Geetha

Dheemanth Nagaraj

Brian S Morris

Massimo Sutera

Sreenivas Mandava

Rajat Agarwal

Tessil Thomas

Kai Cheng

James W Alexander

Chandan Egbert

Jeffrey D Chamberlain

Suresh S Chittor

Amin Firoozshahian

Dennis W Brzezinski

Bongjin Jung

Mahesh Srinivasa Maddury

Omid Azizi

Ganesh Kumar

Ramesh S

Andrew Y Sun

John Peter Stevenson

Ravindra P Saraf

Neil J Achtman

Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

Lazy memory deduplication

Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.

Value of forward state by increasing local caching agent forwarding

Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

Extending a cache coherency snoop broadcast protocol with directory information

In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.

Providing a directory cache for peripheral devices

A memory agent that communicates with another memory agent over links may include error hardware to monitor errors in the links. In some embodiments, the error hardware may include logic to classify the errors into different severity levels, control corrective action based on the severity level of errors, and/or perform various levels of reset based on the severity level of errors. Other embodiments are disclosed and claimed.

Memory agent with error hardware

Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.

Silent data corruption mitigation using error correction code with embedded signaling fault detection

A schematic, system, and flowchart to facilitate storage of directory information for a cache coherency protocol. The protocol allows for at least a single bit of directory information overwriting data stored in a cache coherency unit based at least in part on at least one status bit stored in a storage unit. Likewise, the cache coherency protocol determines whether the cache shared.

Method, system, and apparatus for space efficient cache coherency

Growing community of inventors

Santa Clara, CA, United States of America

Henk G Neefs