Nxp B.v.

Henk Boezen

Peter G Steeneken

Clemens Gerhardus Johannes De Haas

Martin Wagner

Gerhard Koops

Maarten Jacobus Swanenberg

Rajesh Swaminathan

Clemens De Haas

Ramesh G Karpur

Reinout Woltjer

Gerrit Bollen

Inesz Weijland

Krishnaiah Bellamkonda

Frans Bontekoe

Leon Van De Logt

Liquan Fang

According to an example embodiment of the present disclosure, a method is provided for controlling a light-emitting-diode (LED) circuit. The method includes receiving a direct current to direct current (DC-to-DC) control signal at a DC-to-DC converter. A DC voltage is generated from an input DC voltage source. The DC voltage has a voltage level that is set according to the DC-to-DC control signal. The DC voltage is provided to an LED circuit output. The DC voltage level from the DC-to-DC converter is determined. The DC-to-DC converter control signal is generated in response to the determined DC voltage level. The LED circuit is determined to have a short circuit based upon the determined DC voltage. In response to determining that the LED circuit has a short circuit, the DC-to-DC converter is disabled from providing the DC voltage to the output for powering an LED circuit.

LED short circuit protection

One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

Interface for communication between voltage domains

A power supply regulator circuit uses a feedback loop to control current through a first output transistor from a power supply input to a regulated power supply output. The first output transistor is included in an integrated circuit. In order to avoid heating of the integrated circuit in excess of an acceptable level due to permanent supply of a high current through the first transistor, current through a second output transistor in parallel with the first transistor, but outside the integrated circuit is raised when it is detected that the current through the first output transistor exceeds a threshold level. The second output transistor outside the integrated circuit serves to take over supply of a part of the power supply current from first output transistor inside integrated circuit, when long term supply of that part from first output transistor would lead to undesirable heating of the integrated circuit. During a limited time interval a first transistor current above the threshold level is acceptable. During this time interval the current through the second output transistor is raised slowly in order to avoid unpredictable stability problems and the generation of excessive power supply noise.

Electronic circuit with a regulated power supply circuit

An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second header followed by at least one boundary scan test input bit. The bit stream and the clock are extracted and occurrences of the first header and second header are detected. Based on the detected occurrences the boundary scan mode bits and boundary scan input bits are identified and distributed to the electronic circuit, along with the extracted clock, and boundary scan test is performed.

System and method for single terminal boundary scan

A bus driver circuit for driving a bus voltage is provided. The bus driver circuit comprises: a bus line output (CANL) the bus voltage of which is driven by the bus driver circuit; a first transistor (M) having a gate, the voltage at the gate of the first transistor (M) determining the bus voltage at the bus line output (CANL); a first capacitor (C) connected to the gate of the first transistor (M) for driving the voltage at the gate of the first transistor (M); a first switch (S) connecting/disconnecting the first capacitor (C) to a first voltage source (Vgm) via a first RC network comprising at least one resistor and at least one capacitor; and a second switch (S) connecting/disconnecting the first capacitor (C) to a predetermined fixed potential (GND) for discharging the first capacitor (C) via a second RC network comprising at least one resistor and at least one capacitor. The first switch (S) and the second switch (S) are complementarily driven by a signal (TxD) on a data line.

Bus driver circuit

A full duplex, high speed test interface comprises a tester side circuit and a device under test side circuit, each comprising balancing circuits. The balancing circuit of the test side circuit is configured to cancel its own transmitted data at the test side circuit such that the transmitted data does not influence any other signal generated at the test side circuit. Similarly, the balancing circuit of the device under test side circuit is configured to cancel its own transmitted data at the device under test side circuit such that the transmitted data does not influence any other signal generated at the device under test side circuit.

High speed full duplex test interface

The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor (M) in a high voltage deep sub micron process. To provide a circuit arrangement for switching a high side CMOS transistor (M) in a circuit having a very thin gate oxide, produced by a deep sub micron process, a circuit arrangement is proposed for controlling a high side CMOS transistor (M), wherein the high side CMOS transistor (M) is coupled between a high side voltage potential (Vbat) and a control output (OUT) for switching an external device, the high side CMOS transistor (M) is controlled at its gate by a reference potential (Vbat-Vref), which is provided by a high side voltage reference () having a capacitor (C), which is charged for switching on and discharged for switching off the high side CMOS transistor (M).

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Nijmegen, Netherlands

Henk Boezen