Nanjing University of Posts and Telecommunicatins

Nantong Institute of Nanjing University of Posts and Telecommunications Co.,ltd.

Henglu Wang

Yufeng Guo

Zhikuang Cai

Jiafei Yao

Zixuan Wang

Binbin Xu

Zushuai Xie

Guopeng Zhou

Jian Xiao

Jingjing Guo

Jian Song

Haijun Shen

Lu Liu

Ming Wang

Hang Yang

Hongqiang Zhu

Yunbo Wang

Jingqi Yao

Haojie Yu

Xun Xu

Zhenghao Zhao

A reconfigurable MBIST method based on an adaptive March algorithm is provided. The reconfigurable MBIST method automatically reconfigures different algorithm circuits according to external environment and user instructions to satisfy detection requirements for different faults. The provided adaptive March algorithm is capable of adaptively reorganizing algorithms with different complexities, such that dynamic adjustments can be executed between time complexities of the algorithm and fault coverage rates to achieve a good balance, and the static fault coverage rates are high, thereby effectively improving dynamic fault coverage rates.

Reconfigurable MBIST method based on adaptive march algorithm

A circuit for post-binding testing of a 2.5D chiplet includes an interposer-dedicated TAP controller, an interposer test interface circuit and a chiplet test output control circuit. A chiplet test configuration register and its corresponding instructions are newly added for the interposer-dedicated TAP controller. The interposer test interface circuit uses an output control signal of the chiplet test configuration register to select the opening or closing of a test signal channel between an interposer and a chiplet. The chiplet test output control circuit uses the chiplet test configuration register to output a control signal for control of a test data output of the chiplet on the interposer.

Circuit and method for post-binding testing of 2.5D chiplet

Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.

Serial test circuit for controllable Chiplets

The present disclosure relates to the field of design for testability of super-large-scale integrated circuits, and discloses a flexible configurable module (FCM) based chiplet test circuit. The core structure of the circuit is located at an interposer. The test circuit includes FCMs, a control signal configuration module and a test state control module, where the FCM adopts a two-way skew-symmetric structure to implement data transmission in the horizontal direction and the vertical direction; the control signal configuration module is connected to control signals of all the FCMs, so as to control the data transmission directions as well as switch on and switch off states of all the FCMs; and the test state control module controls the shift and update operations of data inside the FCMs and the control signal configuration module.

FCM based chiplet test circuit

The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method. The method includes: dividing non-uniform rectangular grids according to the distribution situation of conductors; determining whether the rectangular grids are boundary cell grids, and marking global numbers and numbers to be solved in sequence; initializing degree of freedom values of all rectangular grids; traversing all rectangular grids, obtaining a linear system of equations, and computing potential function degrees of freedom of all rectangular grids; obtaining an electric field strength function degree of freedom of each cell according to the potential function degree of freedom of each rectangular grid; and dividing a Gaussian surface of each conductor, performing integration of the determined electric field strength function on the Gaussian surface to obtain electric charge, and finally, obtaining main conductor capacitance and coupling capacitance.

Method for extracting parasitic capacitance of interconnection lines of integrated circuit based on discontinuous Galerkin finite element method

A method for preventing a differential cryptanalysis attack is provided. The method is implemented by an adaptive scan chain, a control module, and a plaintext analysis module. The plaintext analysis module controls the adaptive scan chain, so that two plaintexts differing in the last bit of only one byte are input through scan chains with different structures. Consequently, the two input plaintexts for which differential cryptanalysis attack technology originally can be used to crack the key are unable to generate outputs that can be used by the differential cryptanalysis attack technology.

Method for preventing differential cryptanalysis attack

Growing community of inventors

Jiangsu, China

Henglu Wang