Globalfoundries U.S. Inc.

Globalfoundries Inc.

Heng Yang

David C Pritchard

Manjunatha Govinda Prabhu

Hongru Ren

Neha Nayyar

Elizabeth Strehlow

Kai Sun

Salvatore Cimino

Lixia Lei

George Jonathan Kluth

Anurag Mittal

Judson Robert Holt

Daniel James Dechene

Jin Zheng Wallner

James Mazza

Mohamed Rabie

Ahmed Hassan

Anton Tokranov

A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

Planar transistor device comprising at least one layer of a two-dimensional (2D) material

Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devices

An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

IC product comprising a single active fin FinFET device and an electrically inactive fin stress reduction structure

The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Fully depleted devices with slots in active regions

One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

Vertical transistor device comprising a two-dimensional (2D) material positioned in a channel region of the device and methods of making such vertical transistor devices

One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devices

A method of forming a semiconductor device is provided, which includes providing gate structures over an active region and forming a hard mask segment on the active region positioned between a first gate structure and a second gate structure. Cavities are formed in the active region using the gate structures and the hard mask segment as masking features, wherein each cavity has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device. Epitaxial material is grown in the cavities to form substantially uniform epitaxial structures in the active region.

Epitaxial structures of semiconductor devices that are independent of local pattern density

The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.

Dummy gate isolation and method of production thereof

One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.

Auxiliary gate antenna diodes

Devices with slotted active regions

A single critical mask process flow and associated structure eliminate the formation of narrow polysilicon defects at the ends of polysilicon gate arrays, and obviate the need to implement complicated ground rules and post-design fill methods to avoid generation of the defects.

Growing community of inventors

Rexford, NY, United States of America

Heng Yang