International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Heng Wu

Kangguo Cheng

Ruilong Xie

Peng Xu

Lan Yu

Juntao Li

Junli Wang

Chen Zhang

Choonghyun Lee

Alexander Reznicek

Dechao Guo

Tenko Yamashita

Ruqiang Bao

Jingyun Zhang

Zuoguang Liu

Julien Frougier

Chun Wing Yeung

Su Chen Fan

Gen Tsutsui

Zhenxing Bi

Robin Hsin Kuo Chao

Brent A Anderson

Xin Miao

Dimitri Houssameddine

Tian Shen

Bruce Bennett Doris

Bahman Hekmatshoartabari

Chanro Park

Hemanth Jagannathan

Xuefeng Liu

Joshua M Rubin

Kevin W Brew

Sebastian Naczas

Karthik Yogendra

Saba Zare

Sung Dae Suk

Shogo Mochizuki

Oleg Gluschenkov

Huai Huang

Jay William Strane

Tao Li

Krishna Thangaraj

Robinhsinku Chao

Reinaldo Ariel Vega

Min Gyu Sung

Cheng-Wei Cheng

Albert M Young

Nanbo Gong

Adra Carr

Eric Raymond Evarts

Teresa Jacqueline Wu

Veeraraghavan S Basker

Nicolas J Loubet

Wenyu Xu

Robert Russell Robison

Andrew Mark Greene

Ravikumar Ramachandran

Albert Manhee Chu

Eric R Miller

Christopher Joseph Waskiewicz

Huimei Zhou

Miaomiao Wang

Jeffrey C Shearer

Ernest Y Wu

Ardasheir Rahman

Kai Zhao

ChoongHyun Lee

Eric Miller

Tianji Zhou

Samuel Sung Shik Choi

A field effect transistor ('FET') stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.

Subtractive source drain contact for stacked devices

A hybrid stacked semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes first channels. The second stack portion is stacked on the first stack portion, and includes second channels. The all-around gate includes a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels. A first gate extension contacts the first gate portion and the second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.

Hybrid stacked field effect transistors

A semiconductor device including a magnetic tunnel junction (MTJ) stack, a first metal line above the MTJ stack and a magnetoelectric material layer above the first metal line. A semiconductor device including an array of magnetic tunnel junction (MTJ) stacks, a first metal line connected physically and electrically to a top electrode of each MTJ stack in a row of the array of MTJ stacks and a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line. A method including forming an array of magnetic tunnel junction (MTJ) stacks, forming a first metal line above a row of the array of MTJ stacks, and forming a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line.

Magnetic tunnel junction device with magnetoelectric assist

A plurality of bit lines corresponding to elements of an input vector intersect a plurality of word lines and a plurality of memristive cells are located at the intersections. At least three cells are grouped together to represent a single matrix element. At least three word lines correspond to each element of an output vector. An A/D converter is coupled to each of the word lines, and for each line, except a first, in each group, a shifter has an input coupled to one of the A/D converters. For each group, an addition-subtraction block adds the output of the A/D converter coupled to the first one of the word lines to outputs of each of the shifters except that for a last one of the word lines, subtracts the output of the last shifter, and outputs a corresponding element of an output vector.

Digital phase change memory (PCM) array for analog computing

A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.

Multi-VT solution for replacement metal gate bonded stacked FET

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Stacked FETS including devices with thick gate oxide

Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers

A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. Wherein the widths Wand Ware different from each other and the lengths Land Lare different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Gate-all-around nanosheet-FET with variable channel geometries for performance optimization

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Nanosheet transistor

A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Looped long channel field-effect transistor

A stacked transistor structure including a top source drain region above a bottom source drain region, wherein a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a replacement spacer surrounding the bottom contact structure, and a top gate spacer separating the replacement spacer from a gate conductor.

Stacked transistors having bottom contact with replacement spacer

Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.

Vertically integrated semiconductor device

Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.

Local interconnect for cross coupling

According to one embodiment of the present invention, a computer-implemented method for dynamically altering a frequency at which data scrubbing is performed on a memory device is disclosed. The computer-implemented method includes monitoring at least one of a temperature and a magnetic field of the memory device. The computer-implemented method further includes, responsive to determining that at least one of the temperature and the magnetic field of the memory device reaches and/or exceeds a predetermined threshold, respectively, increasing the frequency at which data scrubbing is performed on the memory device.

Sensor based memory array data scrubbing

A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor

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Guilderland, NY, United States of America

Heng Wu