Marvell International Limited

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

Heng Tang

Gregory Burd

Zining Wu

Panu Chaichanavong

Nedeljko Varnica

Siu-Hung Fred Au

Tze Lei Poo

Pantas Sutardja

Jun Xu

Aditya Ramamoorthy

Adina Matache

Xueshi Yang

David Geddes

Zaihe Yu

Yu-Yao Chang

Michael Madden

Son Hong Ho

Vincent M Wong

Soichi Isono

Chang Shu

Sean Lee

Panu Chiachanavong

Fred Siu-Hung Au

A method for performing error recovery for data stored on a track of a storage device, in which the method includes: receiving a request to read the data from the storage device, identifying a plurality of sectors of the track to be read in response to the request, reading the data from the plurality of sectors of the track and parity data, based on the data read from the plurality of sectors, determining whether any of the plurality of sectors corresponds to a failed sector, and recovering a portion of the data from the failed sector using the parity data and portions of the data stored in remaining ones of the plurality of sectors.

Error correction for storage devices

A method for redundantly storing data includes receiving data at a storage controller, partitioning the data into a plurality of data blocks, generating a first error correction code associated with a first page within the plurality of data blocks, and generating a first redundancy code associated with at least two data blocks within the plurality of data block. The first redundancy code provides additional error recovery if the first error correction code fail. The method further includes storing the plurality of data blocks, the first error correction code, and the first redundancy code across a plurality of solid state storage devices.

Systems and techniques include a method including: receiving a data request for first data stored at a storage device; reading second data from discrete units of storage of the storage device, the second data comprising the first data read from two or more of the discrete units of storage, error correction code redundancies read from the two or more of the discrete units of storage, and parity data read from at least one of the discrete units of storage; detecting, based on the error correction code redundancies, an error in a first portion of the first data stored in one of the two or more of the discrete units of storage; and recovering the first portion of the first data using the parity data and a second portion of the first data read from one or more remaining ones of the two or more of the discrete units of storage.

Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. In one embodiment an apparatus includes a first hardware layer configured to compute a first group of syndrome values from one or more bit values in the codeword and a second hardware layer configured to compute a second group of syndrome values from one or more bit values in the codeword. The apparatus also includes a first physical memory associated with the first hardware layer and configured to store the first group of syndrome values until the syndrome values change due to a change in a codeword bit value. The apparatus also includes a second physical memory associated with the second hardware layer and configured to store the second group of syndrome values until the syndrome values change due to a change in a codeword bit value.

Syndrome computation in a layered low density parity check decoder

A cryptographic device includes first and second pipeline stages and a pipeline register. The first pipeline stage includes a first byte substitution module configured to (i) receive a first data block including multiple bytes, (ii) perform predetermined mathematical operations on each of the bytes of the first data block, and (iii) for each of the bytes of the first data block, output an intermediate value based on the predetermined mathematical operations. The pipeline register is configured to store the intermediate values. The second pipeline stage includes a second byte substitution module configured to (i) receive the stored intermediate values from the pipeline register, and (ii) generate an output data block, for each intermediate value of the stored intermediate values, by performing predetermined mathematical operations on the intermediate value to generate a corresponding replacement byte of the output data block.

Method and apparatus for pipelined byte substitution in encryption and decryption

Systems and techniques relating to fault tolerant data storage in storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR) and/or storage devices that employ solid state memory, include a method, in some implementations, including: receiving, at a storage controller, a data request for a storage device; reading, in response to the data request, data from discrete units of storage in the storage device, the data comprising stored data read from two or more of the discrete units of storage and parity data read from at least one of the discrete units of storage; detecting an error in the stored data from the reading; and recovering stored data for at least one of the discrete units of storage using the parity data and the stored data read from one or more remaining ones of the two or more of the discrete units of storage.

A system including a first first-in first-out (FIFO) module, a control module, and a second FIFO module. The first FIFO module is configured to receive, from a host, (i) a first block and (ii) a first logical block address corresponding to the first block, where the first block includes first data. The control module is configured to generate a second block, where the second block includes (i) the first data and (ii) the first logical block address. The second FIFO module is configured to receive a third block from the first FIFO module, where the third block includes a second logical block address, and to determine whether the third block is different than the first block depending on whether the second logical block address included in the third block is different than the first logical block address included in the second block.

Systems and methods for data-path protection

A control module includes an encoder module, a detector module, a mapping module, and a difference module. The encoder module receives data, and based on the data, generates a first code word for drives. The drives are associated with a storage system. The detector module detects an addition of a second drive. The encoder module generates a second code word for the second drive. The mapping module: maps physical locations of the data in the drives to logical locations of the first code word; assigns a predetermined value to a logical location corresponding to an unused logical location; and based on the predetermined value, assigns the unused logical location to the second drive. The difference module generates a third code word based on each of the first and second code words. The encoder module, based on the first and third code words, generates a fourth code word for all drives.

System and method for adding a drive to a storage system having multiple drives

Systems and methods are provided for evaluating an asymmetry metric. A receiver receives a synchronization signal, a filtered signal, and a reference signal. A processor processes the synchronization signal and the reference signal to obtain a peak indicator signal, identifies a first set of values and a second set of values from the filtered signal based at least in part on the peak indicator signal, and evaluates an asymmetry metric from the first set of values and the second set of values.

Systems and methods for asymmetry detection based on a synchronization mark

An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. The predetermined matrix is represented by a two-dimensional grid of elements. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.

Apparatus for encoding and decoding using sparse matrices

A hardware architecture for encryption and decryption device can improve the encryption and decryption data rate by using parallel processing, and pipeline operation, and save footprint by sharing hardware components. The hardware architecture can also be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit to encrypt a second portion of the array of data blocks, and a data block combiner to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks.

Method and apparatus of high speed encryption and decryption

Systems and techniques relating to storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR), can include a device, which includes: circuitry configured to write stored data and parity data to discrete portions of a Shingled Magnetic Recording (SMR) track in a SMR storage device; and circuitry configured to recover stored data for one of the discrete portions of the SMR track using the parity data and the stored data read from remaining ones of the discrete portions of the SMR track.

A system including a first filter module configured to receive an input signal including (i) a first shift in a DC level of the input signal and (ii) a second shift in the DC level of the input signal. The first shift has (i) a first magnitude and (ii) a first duration. The second shift has (i) a second magnitude and (ii) a second duration. The second magnitude is different than the first magnitude. The second duration is greater than the first duration. The first filter module is configured to pass the first shift. The second filter module is configured to detect one or more of (i) the first shift and (ii) the second shift, and in response to detecting one or more of (i) the first shift and (ii) the second shift, filter one or more of (i) the first shift and (ii) the second shift.

System and method for detecting and correcting shift in a DC level of an input signal

In one embodiment a data decoding apparatus includes first and second decoding blocks configured to decode codeword bits in a first mode determined by a first probability of non-standard errors and a second mode determined by a second probability of non-standard errors. The apparatus also includes a mode modification logic configured to cause at least one of the first and second decoding blocks to operate in the second mode when the first and second decoding blocks fail to decode the codeword bits in the first mode. In another embodiment, a method includes decoding codeword bits in a first mode determined by a first probability of non-standard errors. When decoding the codeword bits in the first mode fails to decode the codeword bits, the codeword bits are decoded in a second mode determined by a second probability of non-standard errors.

Modification of decoder operating mode based on a probability of non-standard errors in concatenated decoding systems

A transceiver includes a transmitter and a receiver. The transmitter includes an ECC encoder and a data frame generator. The ECC encoder is configured to generate an ECC parity from user data and at least one bit from a syncmark. The data frame generator is configured to generate a data frame for transmission from the syncmark, the user data, and the ECC parity. The receiver includes a detector, an inverter, and a decoder. The detector is configured to detect a received syncmark in a received data frame. The received data frame includes the received syncmark, received user data, and received ECC parity. The inverter is configured to selectively invert a sequence. The sequence includes the received user data, the received ECC parity, and at least one bit from the received syncmark. The decoder is configured to decode one of the sequence or the inverted sequence.

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Sunnyvale, CA, United States of America

Heng Tang