United Microelectronics Corp.

Heng Sheng Huang

Kun-Luh Chen

Te-Sun Wu

Wood Wu

Han-Shen Lo

An improved process of fabricating a read only memory device (ROM's) wherein the buried N+ lines have desirable very narrow widths and are closely spaced. The process provides that masking stripes are formed with vertical sidewalls and that spacers are formed on the sidewalls. The areas between the spacers are filled in. The spacers are etched away to form narrow closely spaced openings. Ions are implanted through the openings to form closely spaced buried lines.

Process for producing very narrow buried bit lines for non-volatile

A process of fabricating a semiconductor device on a substrate with closely spaced high density conductive lines is provided. A thin insulating layer is formed on the surface of a substrate. Next, a blanket conductive layer and a blanket masking layer are deposited over the first insulating layer. Using conventional photolithography processes and plasma etching, elongated spaced parallel masking lines with vertical sidewalls are formed in the masking layer. A blanket polycrystalline silicon layer is deposited on the masking lines and the exposed areas of the conductive layer. Next, the blanket polycrystalline silicon layer is anisotrophically etched to form spacers on the vertical sidewalls of the masking lines. A second planarized masking layer is formed over the spacers and masking lines. The polycrystalline silicon spacers and the underlying first polycrystalline silicon layer are anisotrophically etched to form the closely spaced conductive lines in the first polycrystalline silicon layer. A coating of electrically isolating material is formed between and over the conductive lines.

Process for producing high density conductive lines

This inventions provides a method to form metal lines with smaller line pitches than is possible using the conventional photolithographic single coating process. This invention provides for a double photolithographic process where the surface is coated, exposed and developed twice to form two sets of resist patterns. These resist patterns are used to form metal lines over all the buried bit lines. These metal lines provide better masking of the bit lines from the code implants thereby reducing bit line resistance and increasing ROM read speed.

Process for producing non-volatile memory devices having closely spaced

A cost-effective and manufacturable method for producing ROM integrated circuits with closely-spaced self-aligned conductive lines, on the order of 0.3 micrometers apart, is described. Parallel, conductive semiconductor device structures are formed in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A first conductive polysilicon layer is formed over the insulating layer. The first conductive polysilicon layer is patterned to form first polysilicon conductor lines which are parallel to each other, and orthogonal to the parallel, conductive semiconductor device structures. A first silicon oxide layer is formed on and between the first polysilicon conductor lines. The first silicon oxide layer is anisotropically etched to produce sidewall structures on the first polysilicon conductor lines. A second silicon oxide layer is formed on and between the first polysilicon conductor lines. A second conductive polysilicon layer is formed over the first polysilicon conductor lines and in openings between the first polysilicon conductor lines. The second conductive polysilicon layer is etched back to form second polysilicon conductor lines, parallel to, between and self-aligned with the first polysilicon conductor lines, and separated from the first polysilicon conductor lines by width of the sidewall structures.

Growing community of inventors

Taipei, Taiwan

Heng Sheng Huang