Innolux Corporation

Heng-Shen Yeh

Kuo-Jung Fan

Cheng-Chi Wang

Chuan-Ming Yeh

Wen-Hsiang Liao

Hung-Sheng Chou

Hung-I Tseng

Yu-Jen Chang

Tzu-Yen Chiu

Ching-Wei Chen

Sheng-Hui Chiu

The embodiment of the disclosure provides a composite layer circuit element of an electronic device. The composite layer circuit element includes a first dielectric layer, a first circuit layer and a second dielectric layer. The first circuit layer is disposed on the first dielectric layer, and the second dielectric layer is disposed on the first circuit layer. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer in a cross section view.

Composite layer circuit element

A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer, a first dielectric layer disposed on the first metal layer, a second metal layer disposed on the first dielectric layer, and a second dielectric layer disposed on the second metal layer. A coefficient of thermal expansion of the first dielectric layer is less than a coefficient of thermal expansion of the second dielectric layer.

Redistribution layer structure

A method of manufacturing an electronic device includes providing a substrate, providing an intermediate layer on the substrate, and providing an isolation layer on the intermediate layer. The substrate includes an active region and a peripheral region. The peripheral region is adjacent to the active region, and the ratio of the area of the active region to the area of the substrate surface is between 75% and 92%. The isolation layer includes a first surface and at least one slope. The first surface of the isolation layer is correspondingly disposed in the active region. The at least one slope of the isolation layer is correspondingly disposed in the peripheral region and at a first angle with respect to the substrate surface.

Method of manufacturing electronic device with reduced substrate warpage

A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.

Manufacturing method of package structure of electronic device

A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer and a first dielectric layer disposed on the first metal layer. A range of a difference between a coefficient of thermal expansion of the first dielectric layer and a coefficient of thermal expansion of the first metal layer is 0% to 70% of the coefficient of thermal expansion of the first dielectric layer.

A redistribution layer structure and the manufacturing method thereof are provided. The redistribution layer structure includes a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer. The first dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the second metal layer. A chemical resistance of the first dielectric layer is greater than a chemical resistance of the second dielectric layer.

Redistribution layer structure and manufacturing method thereof

The embodiment of the disclosure provides a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element includes the following. A carrier is provided. A first dielectric layer is formed on the carrier, and the first dielectric layer is patterned. The carrier on which the first dielectric layer is formed is disposed on a first curved-surface mold, and the first dielectric layer is cured. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned. The carrier on which the first dielectric layer and the second dielectric layer are formed is disposed on a second curved-surface mold, and the second dielectric layer is cured. A thickness of a projection of the first curved-surface mold is smaller than a thickness of a projection of the second curved-surface mold.

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Miao-Li County, Taiwan

Heng-Shen Yeh