International Business Machines Corporation

Shanghai Huali Integrated Circuit Corporation

Boe Technology Group Co., Ltd.

Lenovo (beijing) Limited

T-head (shanghai) Semiconductor Co., Ltd.

Huawei Technologies Co., Limited

Beijing Lenovo Software Ltd.

Alibaba (china) Co., Ltd.

Generon (shanghai) Corporation Ltd.

Heng Liu

Ke Wei Wei

Shuo Li

Xin Yang

Yan Lu

Tianpeng Guan

Jianghua Leng

Peng Fei Gou

Zhigang Yang

Chen Qian

Hongzhong Zheng

Yang Fan Liu

Zhen Peng Zuo

Shuangchen Li

Qian Zhao

Tianchan Guan

Shuang Ys Yu

Xiaobo Wang

Dimin Niu

Xiang Sean Zhou

Hong Mei Zhang

Hong Min

Li Ping Yang

Qi Zhang

You-Chin Gene Fuh

He Wang

Peter Bendel

Yingjie Li

Liping Lei

Xiaoqiang Yan

Wei Han

Honglei Zhang

Xiao Xiao Chen

Jian Wei Zhang

Zhigang Li

Yufei Li

Jin Jiang

Xiaoying Meng

Shan Wang

Zhihua Huang

Yuliang Huang

Yawen Zhang

Meichi M Lin

Liu Wang

Zhenyu Shi

Fei Cheng

Michael Schenker

Dongdong Wu

ZeQiang Xiao

Lintao Lei

Shuangcheng Li

Ji Gao Fu

Huimin Che

Mingyu Yu

Embodiments of the present application disclose an audio matching method and a related device. The audio matching method includes: obtaining audio data and video data; extracting to-be-recognized audio information from the audio data; extracting lip movement information of N users from the video data, where N is an integer greater than 1; inputting the to-be-recognized audio information and the lip movement information of the N users into a target feature matching model, to obtain a matching degree between each of the lip movement information of the N users and the to-be-recognized audio information; and determining a user corresponding to the lip movement information of the user with the highest matching degree as the target user to which the to-be-recognized audio information belongs.

Audio matching method and related device for robot control based on calculating a rotation angle

A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

Method for making semi-floating gate transistor with three-gate structure

An approach is provided in which a method, system, and program product analyze, while training a machine learning model, a set of first data transformation operators in a first data preparation pipeline that generates a plurality of constructed features from a set of training data. The method, system, and program product create a plurality of second data preparation pipelines from the first data preparation pipeline, wherein the set of first data transformation operators are converted to a set of second data transformation operators and each assigned to one of the plurality of second data preparation pipelines. The method, system, and program product deploy the plurality of second data preparation pipelines to a runtime system.

Auto feature preparation for high performance online inferencing

The present application discloses a semi-floating gate memory device, which is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer, a source region and a drain region are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. The present application further discloses a method for fabricating the semi-floating gate memory device.

Semi-floating gate memory device and method for fabricating the same

An image display method includes: displaying, on a user interface, a first image loaded into a first image container in a sliding container; adding a second image container to the sliding container in response to an image switching instruction; loading a second image into the second image container, and the second image being an image located behind the first image in a queue of images to be played; and displaying the second image on the user interface.

Sliding image container switching display method, device, and storage medium

The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

Semi-floating gate device

A method for processing a plurality of queries is provided according to embodiments of the present disclosure. In this method, based on a plurality of queries and an execution plan for the plurality of quires, a plurality of record identification (ID) numbers can be stored into a pool in a numerical order. Each of the plurality of record ID numbers can identify a data record in a database. Then, the execution plan can be performed to batch a plurality of data records corresponding to the plurality of record ID numbers in the database based on a distribution of the plurality of record ID numbers in the pool.

Query processing

Disclosed are a method for switching a theme of an application and an electronic device, which belong to the field of electronic technologies. The electronic device receives a theme switching request for a first application in the electronic device. The theme switching request includes an indication for a target theme. In response to the theme switching request, the electronic device switches a theme of the first application to the target theme, and switches a theme of a second application having an association relationship with the first application in the electronic device to the target theme.

Method for switching theme of application and electronic device

This specification describes methods and systems for accelerating attribute data access for graph neural network (GNN) processing. An example method includes: receiving a root node identifier corresponding to a node in a graph for GNN processing; determining one or more candidate node identifiers according to the root node identifier, wherein attribute data corresponding to the one or more candidate node identifiers are sequentially stored in a memory; and sampling one or more graph node identifiers at least from the one or more candidate node identifiers for the GNN processing.

Access friendly memory architecture of graph neural network sampling

This application describes a hardware accelerator, a computer system, and a method for accelerating Graph Neural Network (GNN) node attribute fetching. The hardware accelerator comprises a GNN attribute processor; and a first memory, wherein the GNN attribute processor is configured to: receive a graph node identifier; determine a target memory address within the first memory based on the graph node identifier; determine, based on the received graph node identifier, whether attribute data corresponding to the received graph node identifier is cached in the first memory at the target memory address; and in response to determining that the attribute data is not cached in the first memory: fetch the attribute data from a second memory, and write the fetched attribute data into the first memory at the target memory address.

Graph neural network accelerator with attribute caching

Various embodiments of the present disclosure relate to a computer-implemented method, a system, and a storage medium, where a graph stored in a computing system is logically divided into subgraphs, the subgraphs are stored on different interconnected (or coupled) devices in the computing system, and nodes of the subgraphs include hub nodes connected to adjacent subgraphs. Each device stores attributes and node structure information of the hub nodes of the subgraphs into other devices, and software or hardware prefetch engine on the device prefetches attributes and node structure information associated with a sampled node. A prefetcher on a device interfacing with the interconnected (or coupled) devices may further prefetch attributes and node structure information of nodes of the subgraphs on other devices. A traffic monitor is provided on an interface device to monitor traffic. When the traffic is small, the interface device prefetches node attributes and node structure information.

Computer-implemented method, system, and storage medium for prefetching in a distributed graph architecture

The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

Double control gate semi-floating gate transistor and method for preparing the same

In an approach, a processor receives an input indicative of a set of registers, the set of registers being configured for obtaining output data from a design-under-test (DUT) in a field-programmable gate array (FPGA) module. A processor executes a set of instructions for monitoring the output data in the set of registers;. A processor generates data indicative of at least one portion of changes of the output data in the set of registers during the execution of the set of instructions. A processor causes a separate machine to analyze the data via utilizing an interface to send the data to the separate machine.

Heterogeneous-computing based emulator

Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: receiving, by a production database, a query statement for processing by the production database; the production database in performing runtime execution processing of the query statement identifying one or more query statement value of the query statement; the production database in performing runtime execution processing of the query statement establishing, using a predictive model, an access path based on the identified one or more query statement value; and the production database using the established access path in performing runtime execution processing of the query statement.

Multiple access path selection by machine learning

The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware model that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.

Hardware incremental model checking verification

Growing community of inventors

Beijing, China

Heng Liu