Pmc-sierra, Inc.

Pmc-sierra Us, Inc.

Microsemi Storage Solutions, Inc.

Heng Liao

Larrie Simon Carr

Kuan Hua Tan

Stacy W Nichols

Cheng Yi

Zhao Wu

Calvin Leung

Keith Graham Shaw

Praveen Alexander

Shahram Davari

Paul Chong

Vernon Robert Little

Patrick Neil Bailey

Babysaroja Annem

Kevin Huscroft

Xiaofeng Wang

Nicholas Kuefler

Zhongzhi Liu

Truong Nguyen

Nicolas Kuefler

SAS expanders are commonly used within a SAS network topology to allow multiple disk drives (targets) to connect to multiple host devices (initiators). A connection between an initiator and a target is setup inside an expander on the pathway between the initiator and the target. A source device sends a connection request message called an open address frame using in-band signaling. The expander processes the open address frame and forwards an modified open address frame to the next expander in the path or to the final destination device.

Method and apparatus for SAS open address frame processing in SAS expanders

A method and apparatus are disclosed for management of linked lists within a dynamic queue system. In a dynamic queue system where a central memory is shared amongst a set of queues, the method organizes the linked list structures of the queues. The linked list pointers of the queues are organized over a set of single port memories. Memory for the queue entries is allocated in an alternating fashion, which allows the method to provide per-cycle access to queues while reducing the footprint of the memory elements used for maintaining the linked list structures. The method disclosed reduces the overall memory requirements for the design and implementation of queue systems with multiple queues sharing a common pool of memory.

Management of linked lists within a dynamic queue system

The present invention is directed at a method and apparatus for determining a distributed Serial Attached Small computer system interface (SAS) topology in a storage network system. Once a SAS storage network element, such as a SAS Expander, receives notification that a downstream SAS topology has changed, the SAS Expander queries all downstream SAS Expanders to update its route table.

Method and apparatus for distributed topology function in serial attached small computer system interface (SAS)

A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.

DMA address translation scheme and cache with modified scatter gather element including SG list and descriptor tables

A system and method for providing redundant access paths to a storage device make use of a processor to analyze instructions received from hosts to allow for command queuing, host switching, and command replacement where necessary. The system allows for either Serially Attached SCSI or Serial ATA hard drives to be connected to the same topology and to require no host intervention on the coordination of drive access in a multi-host environment. A single ported SATA device can then appear multi-ported and can support a redundant architecture within a SAS topology.

Apparatus for interconnecting hosts with storage devices

Broadcast primitive filtering in a SAS expander using virtual domains. The virtual domains can be non-overlapping or overlapping logical subsets of the physical topology, or a logical construct based on the membership of a device within a group. Broadcast event propagation is handled in accordance with predetermined policies associated with the virtual domains. These policies can, for example, include limiting the broadcast traffic within the boundaries of the logical zones defined by the subsets, or routing the broadcast events in accordance with access policies, or privileges, associated with the group.

Method and apparatus for broadcast primitive filtering in SAS

A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.

Connection management in serial attached SCSI (SAS) expanders

A method and system are provided for broadcast message filtering in SAS expanders. Common SAS topology defined by ANSI T10 specification only supports spanning tree topology (without loops) interconnection among multiple end devices and expander devices. Broadcast message filtering provides a mechanism to selectively discard broadcast messages, or primitives, in the SAS expanders to break the infinite loop path that broadcast primitives can traverse. This enables new SAS physical topologies with loops that are otherwise difficult or impossible to realize using SAS expanders that handle primitive broadcasts according to the definition of the SAS standard. By allowing redundant paths in a SAS topology, the problem of infinite broadcast flooding in SAS topology is reduced. Selectively forwarding broadcast messages can be based on whether the broadcast was originated at the source phy, or received by the source phy, or based on whether the source phy is a filtered phy.

Serial attached SCSI broadcast primitive processor filtering for loop architectures

A method and apparatus are provided for finding the maxima and minima from a set of inputs data. Given a master set K[0 . . . N&#x2212;1] of N keys, the current invention can pre-compute a comparison matrix, find the maximum key Kor minimum key Kfrom the master set K[0 . . . N&#x2212;1] and indicate the key position index Pof the maximum key or Pof the minimum key. Given a subset S[0 . . . M&#x2212;1] of M keys where the subset S[0 . . . M&#x2212;1] belongs to the master set K[0 . . . N&#x2212;1], the current invention can also find the maximum key Sor minimum key Sfrom the subset S[0 . . . M&#x2212;1] and indicate the reference key position index Pof the maxima Sor Pof the minima Sin the master set K[0 . . . N&#x2212;1]. The current invention can also find a specific rank of key (example 5th largest key or 6th smallest key) and return the reference key index position in the master set K[0 . . . N&#x2212;1].

Method and apparatus for finding subset maxima and minima in SAS expanders and related devices

Methods and devices for controlling and managing data flow and data transmission rates. A feedback mechanism is used in conjunction with measuring output transmission rates to control the input transmission rates, changing conditions can be accounted for an excess output transmission capacity can be shared among numerous input ports. Similarly, by using maximum and minimum rates which can be requested from an output port, minimum transmission rates can be guaranteed for high priority traffic while capping maximum output rates for low priority traffic. By combining the two ideas of feedback rate control and placing maximum requestable transmission rates, a more equitable output sharing mechanism arises. The measured output transmission rate is used to control and recalculate the maximum requestable output transmission rate for incoming flows, thereby allowing for changing network and data flow conditions.

Feedback priority modulation rate controller

A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

Logical address direct memory access with multiple concurrent physical ports and internal switching

A method and apparatus are disclosed for implementing STP flow control in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. Connections to a SATA HDD are supported using SATA Tunnelling Protocol (STP), which allows SATA traffic to be carried over a SAS network topology. Flow control in a STP connection is applied through a set of special SATA primitives, both for forward and backward flow control. A method is described herein in which STP flow control is supported without the use of a SATA link layer state machine. This allows STP flow control to be terminated on a hop-by-hop basis without knowing the data channel direction or maintaining a SATA link state machine, and while minimizing gate count.

Serial tunneling protocol (STP) flow control in SAS expanders without SATA link state machine

A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.

On-chip shared memory based device architecture

A multi-port switch and a method of command switching using such a switch. Multiple virtual targets provide multiple hosts with access to the physical target device attached to the target interface of the switch. The switch intelligently dispatches operations received by the virtual targets to the physical storage target device to provide shared access. In doing so, the communication between the switch and the physical target can fully comply with the SATA protocol without the physical target being aware that the operations have originated from multiple physical hosts, and without the multiple physical hosts being aware of the shared nature of the physical SATA target device.

Command switching for multiple initiator access to a SATA drive

A receive virtual concatenation processor (processor) is adapted to receive time-slot interleaved data carried over SONET/SDH frames. The processor first generates per time-slot data and subsequently generates per channel data. The processor supports virtual concatenation, contiguous concatenation as well as mixed concatenation in which some channels are contiguously concatenated and others are virtually concatenated. The processor supports virtual concatenation at both STS-1 and STS-3c granularities and with arbitrary differential delay among constituent time-slots. The processor supports contiguous concatenation with any multiple of STS-3c granularity. The processor is highly scalable to support multiple channels and different frame sizes such as STS-12, STS-48, STS-192, etc.

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Belcarra, Canada

Heng Liao