Freescale Semiconductor,inc.

Motorola Corporation

Osram Opto Semiconductors Gmbh

Technic, Inc.

Heng Keong Yip

Wai Yew Lo

Lan Chu Tan

Kevin John Hess

Chee Seng Foong

Chu-Chung Lee

Tu-Anh N Tran

Thoon Khin Chang

Kian Leong Chin

Hei Ming Shiu

On Lok Chau

Michael D Gernon

Aminuddin Ismail

Gor Amie Lai

James Patrick Johnston

Patrick Johnston

Duane W Endicott

A method of producing a chip module includes providing a carrier; arranging semiconductor chips on the carrier; applying an electrically insulating material on the carrier; and structuring the carrier such that the chip module is provided, wherein the chip module includes separate carrier sections produced by structuring the carrier, the carrier sections of the chip module connected by the electrically insulating material.

Production of a chip module

An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Integrated circuit package with voltage distributor

A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels.

Heat spreader for center gate molding

A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer. An electrical distribution layer is formed over the active side of the first IC and the conductive layer and conductive balls are attached to the electrical distribution layer. The conductive balls allow electrical interconnection to the first and second integrated circuits.

Method of forming stacked die package

A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

Semiconductor wafer with improved crack protection

A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A second etching operation is performed on the metal layer to form the solder pad. A solder mask is formed on the substrate and a portion of the solder pad.

Method of making solder pad

An array QFN package () includes a first semiconductor package () and a lead frame () having a plurality of leads (). A first IC die () is attached on a first side to the first semiconductor package () and is electrically connected to the leads () of the lead frame (). A mold compound () encapsulates the first IC die (), a portion of the first semiconductor package () and a portion of the leads () such that a plurality of I/O terminals () on the semiconductor package () is exposed.

Array quad flat no-lead package and method of forming same

A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

Method for forming reinforced interconnects on a substrate

A flip-chip bump carrier type package is formed by providing a sheet of metal foil and forming cavities in a first surface of the sheet. The cavities are plated with a conductive metal to form external interconnects. An insulating film is formed over the metal foil first surface and the plated cavities and then vias are formed in the insulating film. The vias contact respective ones of the plated cavities. The vias are then plated and a solder resist film is formed over the insulating film and the plated vias. The solder resist film is processed to form exposed areas above the vias, which areas are then plated with a conductive metal. A bumped semiconductor die is attached to the first surface of the metal foil, where the die bumps contact respective ones of the plated, exposed areas, which electrically connects the die to the plated cavities. Finally, the sheet of metal foil is removed so that outer surfaces of the plated cavities are exposed. As stated above, the plated cavity outer surfaces form electrical interconnects between the die and a printed wiring board.

Method of forming flip-chip bump carrier type package

A method of forming a semiconductor package (and) includes providing a substrate () having a die pad and bond pads on a first surface () and conductive pads (and) on a second surface (). An integrated circuit (IC) die () is attached to the die pad and the first surface () of the substrate () is attached to a lead frame (). The substrate () is electrically connected to the lead frame (), and the IC die () is electrically connected to the substrate () and the lead frame (). The IC die (), the electrical connections (and), a portion of the substrate () and a portion of the lead frame () are encapsulated with a mold compound (), forming a stackable package (). The conductive pads (and) on the second surface () of the substrate () are not encapsulated by the mold compound ().

Method of forming stackable package

A method of making an exposed-pad ball-grid array package () includes applying a conductive sheet () to an adhesive tape (). Stamping the conductive sheet () to form a die pad () and separating the remainder () of the sheet from the adhesive tape () so that only the die pad () remains on the adhesive tape (). A substrate () is applied to the adhesive tape () proximate to the die pad (). A die () is attached to the die pad () and electrically coupled to the substrate (). An encapsulant () is formed around at least a portion of the die (), the die pad () and the substrate () above the adhesive tape (). The adhesive tape () is removed from the die pad (), substrate () and encapsulant (). Conductive balls () are attached to the substrate ().

Method of making exposed pad ball grid array package

New formulations for the electrodeposition of a dense, reflective tin or tin-lead alloy on a cathode have been developed. Such electrodeposition solutions are partially comprised of an additive which is comprised of at least one nonionic surfactant which is electrolyzed prior to starting the electrodeposition process. The electrodeposition solution is also comprised of an amount of an aliphatic dialdehyde kept low enough so that the solder deposits contain no more than 500 ppm of co-electrodeposited carbon. The additive and the aliphatic dialdehyde is mixed with a solution comprised of an alkane or alkanol sulfonic acid and a tin alkane or alkanol sulfonate or a mixture of a tin and lead alkane or alkanol sulfonate to form an electrodeposition solution. A dense, reflective finish is then electrodeposited on a cathode by using such an electrodeposition solution.

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Selangor, Malaysia

Heng Keong Yip