Taiwan Semiconductor Manufacturing Comp. Ltd.

Heng-Kai Liu

Chien-Wen Chen

Kong-Beng Thei

Chin-Shen Lin

Mu-Jen Huang

Yu-Sian Jiang

Shih-Kai Lin

Ming-Jer Chiu

Chih-Tsung Yao

Harry Chuang

Hsien Yu-Tseng

Harry-Hak-Lay Chuang

Hsien-Yu Tseng

A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N&#x2212;1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Method, system and computer readable medium using stitching for mask assignment of patterns

A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

Wiring layout having differently shaped vias

EDA tool and method, and integrated circuit formed by the method

Method for improving design window

Growing community of inventors

Pingzhen, Taiwan

Heng-Kai Liu