Texas Instruments Corporation

Heng-Chih Lin

Baher S Haroun

Ranjit Gharpurey

Chien-Chung Chen

Anand Ganesh Dabak

Anuj Batra

Jaiganesh Balakrishnan

Abdellatif Bellaouar

David Barry Scott

Solti Peng

Paul H Fontaine

Tim Foo

Charvaka Duvvury

Petteri Matti Litmanen

Michel Frechette

Paul Aymeric Fontaine

Takumi Nasu

Jin-sheng Wang

Tiang Tun Foo

A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47, Section 15. The UWB system provides a wireless pico area network (PAN) with data payload communication capabilities of 55, 80, 110, 160, 200, 320 and 480 Mb/s. The UWB system employs orthogonal frequency division multiplexing (OFDM) and uses a total of 122 sub-carriers that are modulated using quadrature phase shift keying (QPSK). Forward error correction coding (convolutional coding) is used with a coding rate of 11/32, 1/2, 5/8 and 3/4.

Time-frequency interleaved orthogonal frequency division multiplexing ultra wide band physical layer

A novel digital attenuator circuit and associated pre-power amplifier (PPA) that substantially increases the dynamic range of the amplifier. Increased dynamic range is achieved by placing a digital current attenuator circuit at the output of the pre-power amplifier so that the minimum possible current output of the transistor switch array of the PPA can be further attenuated. The attenuator functions to split the current between the load and the power supply V(i.e. AC ground) based on device ratio that is controlled digitally via an input power control word. The digital attenuator is constructed as a segmented digitally controlled matrix or cell array comprising at least a pass and bypass matrix or array. The pass matrix controls the amount of current output from the PPA while the bypass matrix controls the amount of current shorted to the AC ground (i.e. power supply). By varying the number of transistors on or off in each matrix, the power output of the PPA can be easily and accurately controlled.

High dynamic range pre-power amplifier incorporating digital attenuator

System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

Ultra-wideband communications system devices

According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that includes a transistor having a gate biased by an output of the gate bias circuit and also having a source connected to an inductor for providing a path to ground for direct current flowing through the transistor. According to another embodiment of the invention, a method for amplifying a signal by an amplifier includes generating a gate bias voltage indicative of a difference between a reference voltage and an output voltage of the amplifier, biasing the gate of the common-gate amplifier with the gate bias voltage, and blocking, by a passive device, alternating current signals from flowing from the source of the transistor to ground.

Method and system for amplifying a signal

A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal. The circuit has an oscillator circuitand a harmonic rejection mixer (HRM). The oscillator circuitincludes at least one 'circuit portion' (FIG.A) configured to receive first and second orthogonal oscillator input signals (two of I, I&#x2212;, Q, Q&#x2212;) having respective first and second phases, and to provide an arbitrarily large number of oscillator output signals (&#x3c6;M) having respective mutually distinct phases that are interpolated between the first and second phases. Harmonic rejection mixeris configured to use the input signal to modulate a combination of the oscillator output signals, the oscillator output signals being respectively weighted so as to provide an emulated sinusoidal signal constituting the reduced harmonic content output signal.

Current interpolation in multi-phase local oscillator for use with harmonic rejection mixer

A current-domain transmitter is configured to receive an input signal and provide a transmitted signal. The transmitter has a plurality of elements, operatively arranged between the input signal and the transmitted signal and configured to represent the input signal with respective electric currents whose respective current magnitudes are each substantially proportional to the input signal. The elements may include a current-steering digital-to-analog converter (DAC), a current mode filter (such as an LPF), a current mode mixer, and/or a current mode amplifier.

Current mode transmitter

An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.

Current switching arrangement for D.A.C. reconstruction filtering

A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.

High-speed signal level detector

The mixer circuit includes a differential rf input driver; a differential local oscillator input circuit coupled to the differential rf input driver; a non-linear load coupled to the differential local oscillator input circuit wherein the non-linear load compensates for non-linearity of the differential rf input driver. The non-linear load has a V-I (voltage-current) transfer function the inverse of the input driver. This improves the mixer linearity without sacrificing the Gain or Noise Figure.

Inverse function method for semiconductor mixer linearity enhancement

The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

Adaptive amplifier output common mode voltage adjustment

A hybrid Nyquist thermometer and sigma delta digital to analog converter is presented. The digital input signal is divided into most significant bits and least significant bits. The most significant bits are converted to a thermometer code. A thermometer element array is controlled by the thermometer code. A fractional value is calculated from the least significant bits and used to dither the first unexercised array element in order to get finer resolution with guaranteed monotonicity.

Guaranteed monotonic digital to analog converter

A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

Wide band, wide operation range, general purpose digital phase locked loop architecture

A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.

Compact, high power supply rejection ratio, low power semiconductor digitally controlled oscillator architecture

A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa. More importantly, the complete switch over only takes two cycles of the targeted clock in the best case once the active clock is turned off, when switching from slow to fast clock; and four target clock cycles in the worst case once the active clock is turned off, when switching from fast to slow clock.

Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time

A semiconductor device ( ) having a substrate routed power supply voltage is disclosed. The semiconductor device ( ) includes a relatively highly doped substrate ( ) and an epitaxial layer ( ) formed over the substrate ( ). In one embodiment ( ), a surrounding conductive structure ( ) is formed on the peripheral edges of the semiconductor device ( ) die. The surrounding conductive structure ( ) is coupled to the substrate ( ). In another embodiment, the back side of the die ( ) is coupled to the conductive portion ( ) of an integrated circuit package. The conductive portion ( ) is coupled to a power supply voltage. In another embodiment ( ), the surrounding conductive structure ( ) is coupled to a power supply voltage by one or more bond pads ( ) formed on, or coupled to, the surrounding conductive structure ( ).

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Plano, TX, United States of America

Heng-Chih Lin