Via Technologies, Inc.

Heng-Chen Ho

Jiin Lai

Kuo-Ping Liu

Hsiang-Yi Huang

Bi-Yun Yeh

Michael Liu

Shu-Tzu Wang

Jacky Tsai

Victor Wu

Frank Lin

Vincent Chang

Chi Hao Chang

Yi-Kuang Wei

Ming-Cheng Tsai

A method and computer system for accessing initialization data stored in a boot memory space. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the memory space and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.

Computer system for accessing initialization data and method therefor

A PLL device of a core logic chip includes a controlled delay circuit having a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals in response to a reference clock signal; a phase detector for generating an adjusting signal according to a phase difference between the reference clock signal and the output clock signals; and a control circuit for asserting a plurality of control signals to the controlled delay lines, respectively, according to the adjusting signal in order to have the delay times of the output clock signals independently adjusted and outputted again by the controlled delay lines. The delay times of the output clock signals can be determined according to a distribution table and further tuned according to a circuitry and a layout of the core logic chip.

Delay phase-locked loop device and clock signal generating method

A method and related apparatus for reordering access requests used to access main memory of a data processing system. The method includes receiving one or more access requests for accessing the memory device in a first predetermined order, and reordering the access requests in a second predetermined order to be processed in a request queue by relocating a first access request to follow a second access request accessing a same memory page to increase processing efficiency. In addition, the relocating is prohibited if it increases a processing latency for a third access request to exceed a predetermined limit.

Method and related apparatus for reordering access requests used to access main memory of a data processing system

A method for a graphics chip to access data stored in a system memory of a computer device is disclosed. The method includes using a memory controller to set a block capacity value; using the memory controller to divide a plurality of read requests corresponding to a predetermined request sequence into a plurality of request groups, wherein a total amount of data required by read requests grouped in each request group is less than the block capacity value; and using the memory controller to adjust a request sequence corresponding to read requests grouped in each request group for retrieving data stored at different N pages so that a memory device only performs N&#x2212;1 page switching operations.

Method for a graphics chip to access data stored in a system memory of a computer device

An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a delay unit for processing one of the bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to the delay unit and a source voltage, and selectively enabled to output the delayed bit signal as a high level, and a pull-down unit electrically connected to the delay unit and a ground voltage, and selectively enabled to output the delayed bit signal as a low level. The comparator is electrically connected to the N counts of output buffers, compares the N counts of bit signals sampled at a first time spot and a second time spot, and generates the delay signal according to the comparing result.

Output circuit and method for reducing simultaneous switching output skew

A method and computer system for accessing initialization data stored in a boot ROM's memory space which is not used by a BIOS contained in the boot ROM. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the boot ROM and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.

A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively multiplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

Computer chip set for computer mother board referencing various clock rates

A method for performing rework test on integrated circuit (IC) packages is provided. By this method, the first step is to remove a selected part of the casing of the IC package to form an opening in the casing to expose the IC chip contained in the casing. Then, an adhesive layer, such as a double adhesive tape, is attached over the casing on the side where the opening is formed. Then, a heat-insulative cover, such as a ceramic cover, is adhered to the double adhesive tape. After this, the entire IC package is mounted by solder on a test circuit board, allowing a function test procedure to be performed on the internal circuitry of the IC chip contained in the casing. During the function test procedure, when necessary, the ceramic cover can be easily and effortlessly detached to allow the test engineer to visually inspect the inside IC chip for any structural problems.

Method of performing rework test on integrated circuit packages

A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively muliplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

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Taipei, Taiwan

Heng-Chen Ho