Nxp B.v.

Koninklijke Phillips Electronics N.v.

Hendrikus Petrus Elisabeth Vranken

Friedrich Hapke

Hendrik Dirk Lodewijk Hollmann

Thomas Franciscus Waayers

Fransiscus Wilhelmus Sijstermans

Andreas Glowatz

David Lelouvier

Herve Fleury

Kornelis Antonius Vissers

Gerardus Arnoldus Antonius Bos

A method () for locating a fault in an integrated circuit () having a plurality of digital outputs coupled to compaction logic () in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the steps of: providing a simulation model of the integrated circuit (); providing the simulation model with a plurality of test patterns (); receiving a plurality of simulated test responses to said test patterns (); defining a plurality of bits in the plurality of responses, said bits defining a signature of the fault (); providing the integrated circuit with a further plurality of test patterns (); receiving a plurality of test responses to said further plurality of test patterns (); and checking the plurality of responses for the presence of the signature (). This method provides improved fault detectability for an IC subjected thereto.

Integrated circuit test method and test apparatus

An integrated circuit (IC) arrangement () comprises an integrated circuit () having a digital circuit portion () with a plurality of digital outputs (), each of the outputs being arranged to provide a test result in a test mode of the integrated circuit (). The arrangement () further comprises space compaction logic () comprising a space compaction network () having a plurality of compaction domains (), each domain being arranged to compact a plurality of test results into a further test result, and a spreading network () coupled between the plurality of digital outputs () and the space compaction network (), the spreading network being arranged to duplicate each test result from the digital outputs () to a number of compaction domains (). This space compaction logic (), which may be located on the ICor external thereto such as on a test apparatus or on a test interface, reduces the risk of fault cancellation or fault aliasing compared to SCLs without spreading network.

Integrated circuit arrangement and design method

A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including 'care' bits and 'don't care' bits. The test vector data is then compressed by comparing corresponding bits of two or more subsequent vectors and merging the two or more vectors into a single vector representative thereof if all of the corresponding bits of the two or more vectors are found to be compatible. Compatibility of two bits is achieved if they do not have specifically incompatible or opposite values.

Methods and apparatus for data compression

An apparatus for testing an integrated circuit is disclosed. The apparatus includes a compactor to compress test responses from a circuit under test that is part of an integrated circuit.

Method and system for selectively masking test responses

A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action is taken if one or more of the multi-bit subfields meet the corresponding conditions.

Data processor and method for using a data processor with debug circuit

In a method for testing a testable electronic device having a first and a second plurality of test a arrangements a first shift register () is used in parallel with a second shift register () to time-multiplex a first test vector () and a second test vector () into a number of smaller test vectors () for provision to the first and second plurality of test arrangements. By varying the size of the first shift register () and the second shift register () a trade-off between the number of pins of the electronic device to be contacted and the required test time can be made. The first shift register () may be coupled to a first buffer register () and second shift register () may be coupled to a second buffer register () for enhanced test data stability. First shift register () and second shift register () can be partitions of a larger shift register. The method can also be used in a reverse way by time-demultiplexing test result vectors into a single vector at the output side of the testable electronic device.

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Eindhoven, Netherlands

Hendrikus Petrus Elisabeth Vranken