U.S. Philips Corporation

Hendrik Vrielink

Jozef L Kessels

Eduard M Van Der Ouderaa

Wijnand J Schoenmakers

Adriaan Willemse

A device for the processing of a data base consisting of a sequence of data records, having a reference memory (140) for a reference data record and a mask memory (142) for a mask data record. In reaction to the successively received data of a data record, these memories can be read in order to activate a comparison. There is provided an indicator element (160) which has a state 'provisionally correct' and which is activated by a starting signal produced by the reception of a data record. If the comparison indicates that an impermissible relationship exists between the content of an element of the data record received and the corresponding element of the reference data record, the indicator element is set to the state 'incorrect'. The data record received is meanwhile stored in a data buffer (100,102). At the end of the reception, the state of the indicator element indicates whether or not the data record may be applied to a user. The data buffer may consist of two buffer sections, each for one complete data record, which alternately operate in a read mode and a write mode.

Device for associative searching in a sequential data stream composed of

The unauthorized reading of program words stored in a memory of a dating processing system is counteracted by supplying the unauthorized reader with nuisance data from a data source instead of program words from the memory. In order to determine whether the memory is being read by an unauthorized reader or by a data processor unit of the system for the execution of the program, use is made of the sequence in which the data processor unit reads the program words from the memory. This sequence deviates from the sequence in which the program words are stored in the memory. Additional information is added to each program word stored in the memory, said additional information containing an indication of a subsequent program word to be read by the data processor unit. On the basis of this additional information it is tested whether the memory is being read in the sequence determined by the data processor, for the execution of the program, or in some other sequence by an unauthorized reader who does not know the sequence determined by the data processor unit.

Arrangement for protecting against the unauthorized reading of program

An integrated sorting device for data words comprises a bidirectional bus (54) to which are connected the address input (AD) of a memory (52), a command register (66) for memory clear, sorting criterion and pointer reset signals, a multiplexer (74) and an address counter (98). In a write mode of operation, data words arriving on the bus address the memory and representations thereof, e.g. binary 1s, are stored therein. Briefly before each such storage operation, the same memory location is read and any representation (DOUT) already stored therein is used to trigger flip-flop (82) to indicate that an overflow condition exists. During a read operation, the address counter addresses the successive memory addresses under the control of an oscillator (88). When a filled memory location is reached, a further flip-flop (94) causes the counter to stop and a 'ready' signal (RDY) is outputted. The counter resumes counting when the relevant memory location has been read completely. The multiplexer feeds the overflow signal and a read termination signal derived from the address counter to the bus.

Sorting device for data words

Signal processor device having a processor module and a conditional interrupt module for use in a multiprocessor system employing these signal processor devices. The processor module has address, data and control inputs and outputs, including an interrupt signal input for receiving an incoming interrupt request signal. The signal processor device has at least one conditional interrupt module in which the identity address of the signal processor is present, said interrupt module having inputs for receiving an incoming external interrupt request signal with corresponding destination address. The conditional interrupt module also has comparators in which its identity address is compared with the destination address. If the addresses agree, an interrupt signal is fed to the interrupt signal input of the processor module. The processor module may also have an interrupt signal output and be provided with an arbitration module to prevent conflicts between several interrupt requests. The provision of the conditional interrupt module enables interrupts to be processed in a multiprocessor system employing a plurality of such devices without all the devices being initially interrupted and without it being necessary to provide a multiplicity of interrupt lines.

Signal processor device with conditional interrupt module and

A multi-source/receiver data processing system has a communication bus of at least one transfer medium. Clock signal generators have different clock frequencies with respect to each other. To prevent sources and/or receivers having a slow clock signal generator from being excluded as rightful participants from an action concerning a communication, the system determines whether said bus is 'ready' for executing an action using first and second detecting means whereby it can allocate a first and a second period of time thereto, respectively. When a source/receiver determines that this second period of time has expired, the bus is indeed ready for this source/receiver and all further source/receivers which have meanwhile determined during their first period of time that the bus in ready, so the bus can be occupied by this action.

Growing community of inventors

Eindhoven, Netherlands

Hendrik Vrielink