U.S. Philips Corporation

Koninklijke Philips Corporation N.V.

Nxp B.v.

Hendrik Ten Pierick

Friedrich E Hahn

Dirk J Teuling

Edward M Ponte

Dirk J A Teuling

Christinus Johannes Van Valburg

Kar B Chan

Johannes A Maas

Gianlorenzo Paoletti

Steven J Koelewijn

Willem J De Haan

Frederik J De Bruijn

Jan G Prummel

Volker Stefan Gierenz

Alko F De Vries

Dirk, J Teuling

An automatic gain control circuit has a gain determination circuit (B) which determines a first gain factor (g), and a first gain controller (B) which controls an amplitude of an input signal (S) with the first gain factor (g) to supply a gain controlled signal (S). A processing circuit (B; B, B) with a predetermined limited dynamic range processes the gain controlled (S) to obtain an output signal (S; S). The automatic gain control circuit further comprises a compensation circuit (B) which determines a second gain factor (dg) based on the first gain factor (g) and input parameters (DL, TR, DV) which define a time variation of the second gain factor (dg), and a second gain controller (B; B) which receives the second gain factor (dg) to obtain a compensated output signal (S) that is substantially compensated for an amplitude change of the gain controlled signal (S) due to a change of the first gain factor (g).

Gain compensation based on a first gain factor and a second gain factor with time-varying compensation

The invention relates to a system () of a control unit () and a logic application (), wherein the control unit () and the logic application () are connected to a system clock, wherein the logic application () comprises a series connection () of logic elements (), wherein, in use, the system clock generates a clock signal () and feeds this clock signal to the control unit () and the logic application (), and wherein the control unit () controls the supply voltage of the series connection () on the basis of the clock signal () such that the delay time of the series connection () is substantially equal to a predetermined value.

Combination of a control unit and a logic application, in which the combination is connected to a system clock

In a waveform generator, a repetitive non-linear waveform is generated by varying the number supplied to a pulse reduction circuit during the repetition period. Consequently, the pulse reduction circuit supplies a number of desired output pulses, which number varies in time corresponding to the varying number. For example, when a lower number is inputted to the pulse reduction circuit during a sub-period of the repetition period, a corresponding lower number of output pulses will be generated. Consequently, a lower number of increment values will be summed or integrated during this sub-period and the waveform changes less steeply.

Generating a non-linear waveform

In a driving circuit ( ) for a semiconductor switching element ( ), a storage time (Ts) of the semiconductor switching element ( ) is measured ( ) to control the semiconductor switching element ( ) such that the storage time (Ts) is kept substantially constant.

Driving circuit for a semiconductor switching element

A time period (Td) is generated with a high accuracy and a high resolution. At a starting instant (ti) of the time period (Td), an analog integration operation (,) is started to generate an integration value (ios). At a certain instant (t,), the analog integration operation is interrupted to start counting (,) clock pulses (Clk). A selected number (N;N,) of clock pulses (Clk) is counted to obtain a sub-period (T,). The analog integration operation is resumed at the end of the sub-period (T,) at the integration value (ios) reached at the start of the sub-period (T,). The analog integration operation finishes at an end instant (td) of the time period (Td) at which the integration value (ios) crosses a reference value (Ref).

Generation of a time period

A position-dependent waveform (WCi) is generated by generating a set of functions (f.sub.l (I1), . . . ,f.sub.p (I1),g.sub.l (If), . . . ,g.sub.r (If)) from position information (I1,If). A sub-set of functions (f.sub.nl (I1), . . . ,f.sub.nq (I1),g.sub.nl (If), . . . ,g.sub.ns (If))is selected from this set of functions (f.sub.l (I1), . . . ,f.sub.p (I1),g.sub.1 (If), . . . ,g.sub.r (If)). Only selected functions associated with the sub-set of functions (f.sub.nl (I1), . . . ,f.sub.nq (I1),g.sub.nl (If), . . . ,g.sub.ns (If)) are each multiplied by an associated coefficient (al, . . . ,aq,bl, . . . ,bs). The selected functions (f.sub.nl (I1), . . . ,f.sub.nq (I1),g.sub.nl (If), . . . ,g.sub.ns (If)) multiplied by an associated coefficient (al, . . . ,aq,bl, . . . ,bs)are added to form the position-dependent waveform (WCi).

Waveform generation

To improve the sharpness of (video) pictures to be displayed on a display screen of a display device, it is known to use scan velocity modulation. The drawback of scan velocity modulation is that an improvement of the (impression of) sharpness is obtained in given types of video signal/pictures only. By starting from the properties of the display tube when improving the (impression of) sharpness of the displayed picture, a much better improvement can be obtained. Information about the relevant display tube is applied to a correction circuit which also receives a video signal-dependent signal. With reference to these input signals, the correction circuit determines whether and how the video signal is to be corrected so as to obtain an ideal picture on the display screen. Reducing the contrast is a first step of restoring the resolution. Modulating the read clock of the video signal is a second step. Using scan velocity modulation is the last step. The correction circuit determines/computes one clock signal which is applied to a contrast control circuit, a clock modulator and a scan velocity modulator, respectively.

Display device including a correction circuit, and correction circuit

One of the problems in display devices is that the black level is different for each type of display tube and is also dependent on temperature and ageing. The display devices hitherto known with black level setting circuits apply one control voltage to the relevant cathode during the field blanking interval, whereafter the cathode current is measured and subsequently compared with a reference current. Subsequently, the black level is adapted until the measured current approximately corresponds to the reference current. The display device now includes a black level setting circuit with a control circuit adapted to successively apply at least two control voltages in a predetermined ratio to the cathode. Moreover, the black level setting circuit includes a correction circuit for supplying a correction value dependent on the ratio between the currents generated in the relevant cathode in response to the at least two control voltages.

Display device including a black level setting circuit

Circuit arrangement including a parabolic generator for supplying a periodic, substantially parabolic signal to an output terminal during a trace time and an arcuate signal generator for supplying an arcuate signal, which has the shape of, for example, a half sine wave, during a retrace time. At the start of the retrace time, the arcuate signal and its derivatives are given values which are substantially equal to the corresponding values of the parabolic signal at the end of the trace time. The arcuate signal generator is adapted to generate the arcuate signal in a time-discrete manner under the control of switching pulses supplied by a pulse circuit. The pulse circuit is adapted to supply a constant number of switching pulses for generating the arcuate signal in spite of variations in the retrace time, so that the arcuate signal and its derivative assume values which are substantially equal to the corresponding values of the parabolic signal at the start of the trace time.

Circuit arrangement for supplying a periodic, substantially parabolic

A picture display device includes a generator for generating a periodical staircase-shaped signal for addressing picture elements on display screen. The initial value of the staircase shape is settable and a stepwise change takes place each time upon the occurrence of clock pulses. The height of the steps is determined by the following measures:

Picture display device including a staircase generator

A field deflection circuit in a picture display device including a sawtooth generator for generating an essentially sawtooth-shaped voltage. The circuit is provided with a storage element in which information is stored under the influence of applied clock pulses. Per field period the number of times when the content of the storage element is changed is reduced to a predetermined number, e.g. because a number of clock pulses is omitted. The clock pulses applied to the sawtooth generator are then distributed as regularly as possible.

Field deflection circuit in a picture display device

A circuit for generating a deflection current through the field deflection coil of a picture display device having a sawtooth generator, a combining stage, a multiplying circuit and an amplifier. Applied to the combining stage is a sawtooth signal generated by the sawtooth generator and a sawtooth signal originating from feedback. The combining stage generates three linear combinations of these input signals. Two linear combinations are applied to the multiplying circuit for obtaining a parabolic signal which is applied to a signal input terminal of the amplifier, whereas the third linear combination is applied to the feedback input terminal of the amplifier. The series arrangement of the deflection coil and a separating capacitor is coupled to the output terminal of the amplifier, a feedback network being included between the said series network and the combining stage.

Growing community of inventors

Eindhoven, Netherlands

Hendrik Ten Pierick